Engineering topics
Publications and source records attributed to Shaw, D. C..
Applications of highly scaled devices in space applications are shown to be limited by hard errors from cosmic rays. Hard errors were first observed in 0.8 (micro)m DRAMs. For feature sizes below 0.5 (micro)m, scaling theory predicts that low power devices will have much lower hard error rates than devices optimized for high speed.
In this paper, total ionizing dose radiation evaluations of the Micron 64 Mb 3.3 V, fast page mode DRAM and the IBM LUNA-ES 16 Mb DRAM are presented. The effects of scaling on total ionizing dose radiation hardness are studied utilizing test structures and a series of 16 Mb DRAMs with different feature sizes from the same manufacturing line. General agreement was found between the threshold voltage shifts of 16 Mb DRAM test structures and the threshold voltage measured on complete circuits using retention time measurements. Retention time measurement data from early radiation doses are shown that allow internal failure modes to be distinguished.
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Strain measurements using X-ray diffraction were performed on irradiated commercial and radiation-hardened metal gate CMOS devices in addition to polysilicon gate NMOS devices. I-V curves were taken and V(ot) and V(it) were separated using the subthreshold slope method for all devices. A correlation has been shown to exist between physical strain relaxation and the electrical properties as a function of radiation dose and recovery. Data shown suggest that the physical response (strain relaxation) in the silicon at the oxide interface is a measure of the type of damage induced and the recovery mechanism. Postradiation measurements of Delta V(it) and Delta V(ot) taken immediately after irradiation support the conclusions of V. Zekeriya and T.-P. Ma (1983) and K. Kasama et al. (1986, 1987); compressive stress at the silicon/SiO2 interface does reduce radiation damage in the device.
Post-irradiation effects (PIE) ranging from normal recovery to catastrophic failure have been observed in integrated circuits during the PIE period. Data presented show failure due to rebound after a 10 krad(Si) dose. In particular, five device types are investigated with varying PIE response. Special attention has been given to the HI1-507A analog multiplexer because its PIE response is extreme. X-ray diffraction has been uniquely employed to measure physical stress in the HI1-507A metallization. An attempt has been made to show a relationship between stress relaxation and radiation effects. All data presented support the current MIL-STD Method 1019.4 but demonstrate the importance of performing PIE measurements, even when mission doses are as low as 10 krad(Si).