Engineering topics

Routh, D. E.

Publications and source records attributed to Routh, D. E..

12 records

NASA NTRS1986

Multifunction Vacuum Chamber for IC Metallization

Vacuum system chamber processing multilayer metallization on integrated circuits (IC's) performs four operations ordinarily done in separated equipment. Chamber etches holes, removes photoresist, cleans by sputter etching, and deposits final layer of metal. Combinedfunction chamber costs less than separate equipment. Chamber avoids exposing integrated circuits to room air and, to oxidation and dust, between steps. Eliminates time spent in transferring circuits from one apparatus to next.

Routh, D. E.↗

NASA NTRS1984

Method for sequentially processing a multi-level interconnect circuit in a vacuum chamber

An apparatus is disclosed which includes a vacuum system having a vacuum chamber in which wafers are processed on rotating turntables. The vacuum chamber is provided with an RF sputtering system and a dc magnetron sputtering system. A gas inlet introduces various gases to the vacuum chamber and creates various gas plasma during the sputtering steps. The rotating turntables insure that the respective wafers are present under the sputtering guns for an average amount of time such that consistency in sputtering and deposition is achieved. By continuous and sequential processing of the wafers in a common vacuum chamber without removal, the adverse affects of exposure to atmospheric conditions are eliminated providing higher quality circuit contacts and functional device.

Routh, D. E.↗

NASA NTRS1984

Pinhole Occulter Facility

The Pinhole Occulter Facility (POF) is designed for X-ray observations of solar activity, coronal structure and solar wind generation, and coronal transients. The four telescopes or positioning counters, the self-deployable 32-m boom, and the pointing-control actuator of the POF are described. The development of the facility is discussed. The configuration of the POF and means of maintaining its attitude control are examined.

Dabbs, J. R.↗

NASA NTRS1982

Method for sequentially processing a multi-level interconnect circuit in a vacuum chamber

The processing of wafer devices to form multilevel interconnects for microelectronic circuits is described. The method is directed to performing the sequential steps of etching the via, removing the photo resist pattern, back sputtering the entire wafer surface and depositing the next layer of interconnect material under common vacuum conditions without exposure to atmospheric conditions. Apparatus for performing the method includes a vacuum system having a vacuum chamber in which wafers are processed on rotating turntables. The vacuum chamber is provided with an RF sputtering system and a DC magnetron sputtering system. A gas inlet is provided in the chamber for the introduction of various gases to the vacuum chamber and the creation of various gas plasma during the sputtering steps.

Routh, D. E.↗

NASA NTRS1980

Multilayer metalization of MOS IC's

Modified ion-bombardment technqiue interconnects MOS circuit elements without affecting circuit parameters. Multilevel metalization involves: surface treatment prior to metalization; first metalization; metal pattern definition and photoresist removal; dielectric deposition; second metalization; and final dielectric deposition.

Bouldin, D. L.↗

NASA NTRS1979

The MSFC complementary metal oxide semiconductor (including multilevel interconnect metallization) process handbook

The fabrication techniques for creation of complementary metal oxide semiconductor integrated circuits at George C. Marshall Space Flight Center are described. Examples of C-MOS integrated circuits manufactured at MSFC are presented with functional descriptions of each. Typical electrical characteristics of both p-channel metal oxide semiconductor and n-channel metal oxide semiconductor discrete devices under given conditions are provided. Procedures design, mask making, packaging, and testing are included.

Bouldin, D. L.↗

NASA NTRS1979

CMOS circuit-fabrication handbook

Report describes complementary metal-oxide-semiconductor (CMOS) process used to fabricate integrated circuits at Marshall Space Flight Center. It also presents general discussions of circuit design, mask making packaging, and testing.

Bouldin, D. L.↗

NASA NTRS1979

Method of construction of a multi-cell solar array

The method of constructing a high voltage, low power, multicell solar array is described. A solar cell base region is formed in a substrate such as but not limited to silicon or sapphire. A protective coating is applied on the base and a patterned etching of the coating and base forms discrete base regions. A semiconductive junction and upper active region are formed in each base region, and defined by photolithography. Thus, discrete cells which are interconnected by metallic electrodes are formed.

Routh, D. E.↗

NASA NTRS1978

Multilevel metallization method for fabricating a metal oxide semiconductor device

An improved method is described of constructing a metal oxide semiconductor device having multiple layers of metal deposited by dc magnetron sputtering at low dc voltages and low substrate temperatures. The method provides multilevel interconnections and cross over between individual circuit elements in integrated circuits without significantly reducing the reliability or seriously affecting the yield.

Hollis, B. R., Jr.↗

NASA NTRS1976

High and low threshold P-channel metal oxide semiconductor process and description of microelectronics facility

The fabrication techniques and detail procedures for creating P-channel Metal-Oxide-Semiconductor (P-MOS) integrated circuits at George C. Marshall Space Flight Center (MSFC) are described. Examples of P-MOS integrated circuits fabricated at MSFC together with functional descriptions of each are given. Typical electrical characteristics of high and low threshold P-MOS discrete devices under given conditions are provided. A general description of MSFC design, mask making, packaging, and testing procedures is included. The capabilities described in this report are being utilized in: (1) research and development of new technology, (2) education of individuals in the various disciplines and technologies of the field of microelectronics, and (3) fabrication of many types of specially designed integrated circuits which are not commercially feasible in small quantities for in-house research and development programs.

Bouldin, D. L.↗

NASA NTRS1972

Maskmaking facilities at the Marshall Space Flight Center

Research and development maskmaking facilities at the Marshall Space Flight Center are described. Information is provided on the level of cleanliness and the environmental control within the various work areas. The available equipment and its function in the maskmaking process are detailed.

Routh, D. E.↗

NASA NTRS1972

Mask and pattern characteristics

The use of the mask and pattern facility to include information on equipment accuracy, limitations, and pattern making capabilities is discussed. An insight is provided into potential areas of pattern applications, the sequence of mask making, as well as possible inputs and outputs available to the user.

Routh, D. E.↗