Engineering topics

Neudeck, Philip G.

Publications and source records attributed to Neudeck, Philip G..

At least 91 records · Page 5

NASA NTRS2003

Surface Characterization of 3C-SiC Mesa Heterofilms: Evidence for Growth by Edge/Corner Nucleation Mechanism

This paper presents the first detailed observations of unique surface morphologies of 3C-Sic films grown on 4W6H-SIC mesas by the step-free surface heteroepitaxy technique. The top surfaces of 3C-Sic films were extensively studied by optical microscopy and atomic force microscopy (AFM) as both film thickness (i.e,, growth time) and growth temperature (i.e., terrace nucleation rate) were varied following complete coverage of each 4W6H mesa by an initial 3C-Sic film. Almost all surface steps observed by AFM were 0.25 nm, the height of a single Si-C bilayer. However, strikingly different step patterns were observed, suggesting that radically different processes dominate the nucleation of new 3C-Sic bilayers on top of existing 3C-Sic film surfaces.

Trunek, Andrew J.↗

NASA NTRS2003

Step Free Surface Heteroepitaxy of 3C-SiC Layers on Patterned 4H/6H-SiC Mesas and Cantilevers

Most SiC devices are implemented in homoepitaxial films grown on 4H/6H-SiC wafers with surfaces 3 degrees to 8 degrees off-axis from the (0001) basal plane. This approach has not prevented many substrate crystal defects from propagating into SiC epilayers, and does not permit the realization of SiC heteropolytype devices. This presentation describes recent advances in SiC epitaxial growth that begun to overcome the above shortcomings for arrays of mesas patterned into on-axis 4H/6H-SiC wafers. First, we demonstrated that atomic-scale surface steps can be completely eliminated from 4H/6H-SiC mesas via on-axis homoepitaxial step-flow growth, forming (0001) basal plane surfaces (up to 0.4 mm x 0.4 mm) for larger than previously thought possible. Step-free surface areas were then extended by growth fo thin lateral cantilevers from the mesa tops. These lateral cantilevers enabled substrate defects to be reduced and relocated in homoepitaxial films in a manner not possible with off-axis SiC growth. Finally, growth of vastly improved 3C-SiC heterofilms was achieved on 4H/6H-SiC mesas using the recently develop step-free surface heteroepitaxy process. These epitaxial growth developments should enable improved homojunction and heterojunction silicon carbide prototype devices.

Neudeck, Philip G.↗

NASA NTRS2002

Method for Growing Low-Defect Single Crystal Heteroepitaxial Films

A method is disclosed for growing high-quality low-defect crystal films heteroepitaxially on substrates that are different than the crystal films. The growth of the first two heteroepitaxial bilayers is performed on a first two-dimensional nucleate island before a second growth of two-dimensional nucleation is allowed to start. The method is particularly suited for the growth of 3C-SiC, 2H-AlN, or 2H-GaN on 6H-SiC, 4H-SiC, or silicon substrates.

Powell, J. Anthony↗

NASA NTRS2002

Confinement of Screw Dislocations to Predetermined Lateral Positions in (0001) 4H-SiC Epilayers Using Homoepitaxial Web Growth

This paper reports initial demonstration of a cantilevered homoepitaxial growth process that places screw dislocations at predetermined lateral positions in on-axis 4H-SiC mesa epilayers. Thin cantilevers were grown extending toward the interior of hollow pre-growth mesa shapes etched into an on-axis 4H-SiC wafer, eventually completely coalescing to form roofed cavities. Each completely coalesced cavity exhibited either: 1) a screw dislocation growth spiral located exactly where final cantilever coalescence occurred, or 2) no growth spiral. The fact that growth spirals are not observed at any other position except the central coalescence point suggests that substrate screw dislocations, initially surrounded by the hollow portion of the pre-growth mesa shape, are relocated to the final coalescence point of the webbed epilayer roof. Molten potassium hydroxide etch studies revealed that properly grown webbed cantilevers exhibited no etch pits, confirming the superior crystal quality of the cantilevers.

Neudeck, Philip G.↗

NASA NTRS2002

Methods for growth of relatively large step-free SiC crystal surfaces

A method for growing arrays of large-area device-size films of step-free (i.e., atomically flat) SiC surfaces for semiconductor electronic device applications is disclosed. This method utilizes a lateral growth process that better overcomes the effect of extended defects in the seed crystal substrate that limited the obtainable step-free area achievable by prior art processes. The step-free SiC surface is particularly suited for the heteroepitaxial growth of 3C (cubic) SiC, AlN, and GaN films used for the fabrication of both surface-sensitive devices (i.e., surface channel field effect transistors such as HEMT's and MOSFET's) as well as high-electric field devices (pn diodes and other solid-state power switching devices) that are sensitive to extended crystal defects.

Neudeck, Philip G.↗

NASA NTRS2002

Enlargement of Step-Free SiC Surfaces by Homoepitaxial Web-Growth of Thin SiC Cantilevers

Lateral homoepitaxial growth of thin cantilevers emanating from mesa patterns that were reactive ion etched into on-axis commercial SiC substrates prior to growth is reported. The thin cantilevers form after pure stepflow growth removes almost all atomic steps from the top surface of a mesa, after which additional adatoms collected by the large step-free surface migrate to the mesa sidewall where they rapidly incorporate into the crystal near the top of the mesa sidewall. The lateral propagation of the step-free cantilevered surface is significantly affected by pregrowth mesa shape and orientation, with the highest lateral expansion rates observed at the inside concave comers of V-shaped pregrowth mesas with arms lengthwise oriented along the {1100} direction. Complete spanning of the interiors of V's and other mesa shapes with concave comers by webbed cantilevers was accomplished. Optical microscopy, synchrotron white beam x-ray topography and atomic force microscopy analysis of webbed regions formed over a micropipe and closed-core screw dislocations show that c-axis propagation of these defects is terminated by the webbing. Despite the nonoptimized process employed in this initial study, webbed surfaces as large as 1.4 x 10(exp -3) square centimeters, more than four times the pregrowth mesa area, were grown. However, the largest webbed surfaces were not completely free of bilayer steps, due to unintentional growth of 3C-SiC that occurred in the nonoptimized process. Further process optimization should enable larger step-free webs to be realized.

Neudeck, Philip G.↗

NASA NTRS2002

Characterization of 3C-SiC Films Grown on 4H- and 6H-SiC Substrate Mesas During Step-Free Surface Heteroepitaxy

This paper reports detailed structural characterization of 3C-SiC heteroepitaxial films grown on 4H- and 6H-SiC mesa surfaces. 3C-SiC heterofilms grown by the "step-free surface heteroepitaxy" process, free of double-positioning boundary (DPB) and stacking-fault (SF) defects, were compared to less-optimized 3C-SiC heterofilms using High Resolution X-ray Diffraction (HRXRD), High Resolution Cross-sectional Transmission Electron Microscopy (HRXTEM), molten potassium hydroxide (KOH) etching, and dry thermal oxidation. The results suggest that step free surface heteroepitaxy enables remarkably benign partial lattice mismatch strain relief during heterofilm growth.

Neudeck, Philip G.↗

NASA NTRS2002

High-Temperature Electronics: A Role for Wide Bandgap Semiconductors?

It is increasingly recognized that semiconductor based electronics that can function at ambient temperatures higher than 150 C without external cooling could greatly benefit a variety of important applications, especially-in the automotive, aerospace, and energy production industries. The fact that wide bandgap semiconductors are capable of electronic functionality at much higher temperatures than silicon has partially fueled their development, particularly in the case of SiC. It appears unlikely that wide bandgap semiconductor devices will find much use in low-power transistor applications until the ambient temperature exceeds approximately 300 C, as commercially available silicon and silicon-on-insulator technologies are already satisfying requirements for digital and analog very large scale integrated circuits in this temperature range. However, practical operation of silicon power devices at ambient temperatures above 200 C appears problematic, as self-heating at higher power levels results in high internal junction temperatures and leakages. Thus, most electronic subsystems that simultaneously require high-temperature and high-power operation will necessarily be realized using wide bandgap devices, once the technology for realizing these devices become sufficiently developed that they become widely available. Technological challenges impeding the realization of beneficial wide bandgap high ambient temperature electronics, including material growth, contacts, and packaging, are briefly discussed.

Neudeck, Philip G.↗

NASA NTRS2002

Growth of Defect-Free 3C-Sic on 4H- and 6H-SIC Mesas Using Step-Free Surface Heteroepitaxy

A new growth process, herein named step-free surface heteroepitaxy, has achieved 3C-SiC films completely free of double positioning boundaries and stacking faults on 4H-SiC and 6H-SiC substrate mesas. The process is based upon the initial 2-dimensional nucleation and lateral expansion of a single island of 3C-SiC on a 4H- or 6H-SiC mesa surface that is completely free of bilayer surface steps. Our experimental results indicate that substrate-epilayer in-plane lattice mismatch (Delta/a = 0.0854% for 3C/4H) is at least partially relieved parallel to the interface in the initial bilayers of the heterofilm, producing an at least partially relaxed 3C-SiC film without dislocations that undesirably thread through the thickness of the epilayer. This result should enable realization of improved 3C-SiC devices.

Neudeck, Philip G.↗

NASA NTRS2001

Growth of Defect-Free 3C-SiC on 4H- and 6H-SiC Mesas Using Step-Free Surface Heteroepitaxy

A new growth process, herein named step-free surface heteroepitaxy, has achieved 3CSiC films completely free of double positioning boundaries and stacking faults on 4H-SiC and 6H-SiC substrate mesas. The process is based upon the initial 2-dimensional nucleation and lateral expansion of a single island of 3C-SiC on a 4H- or 6H-SiC mesa surface that is completely free of bilayer surface steps. Our experimental results indicate that substrate-epilayer in-plane lattice mismatch (delta a/a = 0.0854% for 3C/4H) is at least partially relieved parallel to the interface in the initial bilayers of the heterofilm, producing an at least partially relaxed 3C-SiC film without dislocations that undesirably thread through the thickness of the epilayer. This result should enable realization of improved 3C-SiC devices.

Neudeck, Philip G.↗

NASA NTRS2001

Homoepitaxial "Web Growth" of SiC to Terminate C-Axis Screw Dislocations and Enlarge Step-Free Surfaces

Homoepitaxial CVD growth of thin lateral cantilevers emanating from the edges of mesa patterns dry-etched into on-axis commercial 4H-SiC substrates prior to growth is reported. Cantilevers on the order of a micrometer thick extending tens of micrometers from the edge of a mesa have been grown. The termination of vertically propagating screw dislocations, including a micropipe, that are overgrown by the cantilevers has been demonstrated, in large part because the crystal structure of the cantilevers is established laterally from the mesa sidewalls. This technique could help reduce performance-degrading dislocations in SiC electrical devices.

Neudeck, Philip G.↗

NASA NTRS2001

Packaging Technology Developed for High-Temperature Silicon Carbide Microsystems

High-temperature electronics and sensors are necessary for harsh-environment space and aeronautical applications, such as sensors and electronics for space missions to the inner solar system, sensors for in situ combustion and emission monitoring, and electronics for combustion control for aeronautical and automotive engines. However, these devices cannot be used until they can be packaged in appropriate forms for specific applications. Suitable packaging technology for operation temperatures up to 500 C and beyond is not commercially available. Thus, the development of a systematic high-temperature packaging technology for SiC-based microsystems is essential for both in situ testing and commercializing high-temperature SiC sensors and electronics. In response to these needs, researchers at Glenn innovatively designed, fabricated, and assembled a new prototype electronic package for high-temperature electronic microsystems using ceramic substrates (aluminum nitride and aluminum oxide) and gold (Au) thick-film metallization. Packaging components include a ceramic packaging frame, thick-film metallization-based interconnection system, and a low electrical resistance SiC die-attachment scheme. Both the materials and fabrication process of the basic packaging components have been tested with an in-house-fabricated SiC semiconductor test chip in an oxidizing environment at temperatures from room temperature to 500 C for more than 1000 hr. These test results set lifetime records for both high-temperature electronic packaging and high-temperature electronic device testing. As required, the thick-film-based interconnection system demonstrated low (2.5 times of the room-temperature resistance of the Au conductor) and stable (decreased 3 percent in 1500 hr of continuous testing) electrical resistance at 500 C in an oxidizing environment. Also as required, the electrical isolation impedance between printed wires that were not electrically joined by a wire bond remained high (greater than 0.4 GW) at 500 C in air. The attached SiC diode demonstrated low (less than 3.8 W/mm2) and relatively consistent dynamic resistance from room temperature to 500 C. These results indicate that the prototype package and the compatible die-attach scheme meet the initial design standards for high-temperature, low-power, and long-term operation. This technology will be further developed and evaluated, especially with more mechanical tests of each packaging element for operation at higher temperatures and longer lifetimes.

Chen, Liang-Yu↗

NASA NTRS2001

Microfabricated Chemical Sensors for Aerospace Fire Detection Applications

The detection of fires on-board commercial aircraft is extremely important for safety reasons. Although dependable fire detection equipment presently exists within the cabin, detection of fire within the cargo hold has been less reliable and susceptible to false alarms. A second, independent method of fire detection to complement the conventional smoke detection techniques, such as the measurement of chemical species indicative of a fire, will help reduce false alarms and improve aircraft safety. Although many chemical species are indicative of a fire, two species of particular interest are CO and CO2. This paper discusses microfabricated chemical sensor development tailored to meet the needs of fire safety applications. This development is based on progress in three types of technology: 1) Micromachining and microfabrication (Microsystem) technology to fabricate miniaturized sensors. 2) The use of nanocrystalline materials to develop sensors with improved stability combined with higher sensitivity. 3) The development of high temperature semiconductors, especially silicon carbide. The individual sensor being developed and their level of maturity will be presented.

Hunter, Gary W.↗

NASA NTRS2000

Method For Growth of Crystal Surfaces and Growth of Heteroepitaxial Single Crystal Films Thereon

A method of growing atomically-flat surfaces and high quality low-defect crystal films of semiconductor materials and fabricating improved devices thereon is discussed. The method is also suitable for growing films heteroepitaxially on substrates that are different than the film. The method is particularly suited for growth of elemental semiconductors (such as Si), compounds of Groups III and V elements of the Periodic Table (such as GaN), and compounds and alloys of Group IV elements of the Periodic Table (such as SiC).

Powell, J. Anthony↗

NASA NTRS2000

Thin and Thick Films Materials Based Interconnection Technology for 500 C Operation

Precious metal based thick-film material was used for printed wires, wire bond pads, test lead-attach, and conductive die-attach for high temperature (up to 500 C and beyond) chip level packaging. A SiC Shottky diode with a thin-film coated backside was attached to a ceramic substrate using precious metal based thick-film material as the electrically conductive bonding layer. After a 500-hour soak test in atmospheric oxygen, these basic interconnection elements, including attached test diode survived both electrically and mechanically. The electrical resistance of these interconnections (including thick-film printed wire/pad, bonded wire, and test lead attach) were low and stable at both room and elevated temperatures. The electrical resistance of the die-attach interface estimated by I-V characterization of the attached diode, during and after high temperature heat treatment, remained desirably low over the course of a 500-hour anneal. Further durability testing of this high temperature interconnection technology is also discussed.

Chen, Liang-Yu↗

NASA NTRS2000

600 C Logic Gates Using Silicon Carbide JFET's

Complex electronics and sensors are increasingly being relied on to enhance the capabilities and efficiency of modernjet aircraft. Some of these electronics and sensors monitor and control vital engine components and aerosurfaces that operate at high temperatures above 300 C. However, since today's silicon-based electronics technology cannot function at such high temperatures, these electronics must reside in environmentally controlled areas. This necessitates either the use of long wire runs between sheltered electronics and hot-area sensors and controls, or the fuel cooling of electronics and sensors located in high-temperature areas. Both of these low-temperature-electronics approaches suffer from serious drawbacks in terms of increased weight, decreased fuel efficiency, and reduction of aircraft reliability. A family of high-temperature electronics and sensors that could function in hot areas would enable substantial aircraft performance gains. Especially since, in the future, some turbine-engine electronics may need to function at temperatures as high as 600 C. This paper reports the fabrication and demonstration of the first semiconductor digital logic gates ever to function at 600 C. Key obstacles blocking the realization of useful 600 C turbine engine integrated sensor and control electronics are outlined.

Neudeck, Philip G.↗

NASA NTRS2000

Temperature Distribution Within a Defect-Free Silicon Carbide Diode Predicted by a Computational Model

Most solid-state electronic devices diodes, transistors, and integrated circuits are based on silicon. Although this material works well for many applications, its properties limit its ability to function under extreme high-temperature or high-power operating conditions. Silicon carbide (SiC), with its desirable physical properties, could someday replace silicon for these types of applications. A major roadblock to realizing this potential is the quality of SiC material that can currently be produced. Semiconductors require very uniform, high-quality material, and commercially available SiC tends to suffer from defects in the crystalline structure that have largely been eliminated in silicon. In some power circuits, these defects can focus energy into an extremely small area, leading to overheating that can damage the device. In an effort to better understand the way that these defects affect the electrical performance and reliability of an SiC device in a power circuit, the NASA Glenn Research Center at Lewis Field began an in-house three-dimensional computational modeling effort. The goal is to predict the temperature distributions within a SiC diode structure subjected to the various transient overvoltage breakdown stresses that occur in power management circuits. A commercial computational fluid dynamics computer program (FLUENT-Fluent, Inc., Lebanon, New Hampshire) was used to build a model of a defect-free SiC diode and generate a computational mesh. A typical breakdown power density was applied over 0.5 msec in a heated layer at the junction between the p-type SiC and n-type SiC, and the temperature distribution throughout the diode was then calculated. The peak temperature extracted from the computational model agreed well (within 6 percent) with previous first-order calculations of the maximum expected temperature at the end of the breakdown pulse. This level of agreement is excellent for a model of this type and indicates that three-dimensional computational modeling can provide useful predictions for this class of problem. The model is now being extended to include the effects of crystal defects. The model will provide unique insights into how high the temperature rises in the vicinity of the defects in a diode at various power densities and pulse durations. This information also will help researchers in understanding and designing SiC devices for safe and reliable operation in high-power circuits.

Kuczmarski, Maria A.↗

NASA NTRS2000

Packaging Technology Developed for High-Temperature SiC Sensors and Electronics

A ceramic- and thick-film-materials-based prototype electronic package designed for silicon carbide (SiC) high-temperature sensors and electronics has been successfully tested at 500 C in an oxygen-containing air environment for 500 hours. This package was designed, fabricated, assembled, and electronically evaluated at the NASA Glenn Research Center at Lewis Field with an in-house-fabricated SiC semiconductor test chip. High-temperature electronics and sensors are necessary for harsh-environment space and aeronautical applications, such as space missions to the inner solar system or the emission control electronics and sensors in aeronautical engines. Single-crystal SiC has such excellent physical and chemical material properties that SiC-based semiconductor electronics can operate at temperatures over 600 C, which is significantly higher than the limit for Si-based semiconductor devices. SiC semiconductor chips were recently demonstrated to be operable at temperatures as high as 600 C, but only in the probe station environment because suitable packaging technology for sensors and electronics at temperatures of 500 C and beyond did not exist. Thus, packaging technology for SiC-based sensors and electronics is immediately needed for both application and commercialization of high-temperature SiC sensors and electronics. In response to this need, researchers at Glenn designed, fabricated, and assembled a prototype electronic package for high-temperature electronics, sensors, and microelectromechanical systems (MEMS) using aluminum nitride (AlN) substrate and gold (Au) thick-film materials. This prototype package successfully survived a soak test at 500 C in air for 500 hours. Packaging components tested included thick-film high-temperature metallization, internal wire bonds, external lead bonds, and a SiC diode chip die-attachment. Each test loop, which was composed of thick-film printed wire, wire bond, and lead bond was subjected to a 50-mA direct current for 250 hours at 500 C.

Chen, Liang-Yu↗