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Neudeck, Philip G.

Publications and source records attributed to Neudeck, Philip G..

At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2014

Structural Characterization of Lateral-grown 6H-SiC am-plane Seed Crystals by Hot Wall CVD Epitaxy

The performance of commercially available silicon carbide (SiC) power devices is limited due to inherently high density of screw dislocations (SD), which are necessary for maintaining polytype during boule growth and commercially viable growth rates. The NASA Glenn Research Center (GRC) has recently proposed a new bulk growth process based on axial fiber growth (parallel to the c-axis) followed by lateral expansion (perpendicular to the c-axis) for producing multi-faceted m-plane SiC boules that can potentially produce wafers with as few as one SD per wafer. In order to implement this novel growth technique, the lateral homoepitaxial growth expansion of a SiC fiber without introducing a significant number of additional defects is critical. Lateral expansion is being investigated by hot wall chemical vapor deposition (HWCVD) growth of 6H-SiC am-plane seed crystals (0.8mm x 0.5mm x 15mm) designed to replicate axially grown SiC single crystal fibers. The post-growth crystals exhibit hexagonal morphology with approximately 1500 m (1.5 mm) of total lateral expansion. Preliminary analysis by synchrotron white beam x-ray topography (SWBXT) confirms that the growth was homoepitaxial, matching the polytype of the respective underlying region of the seed crystal. Axial and transverse sections from the as grown crystal samples were characterized in detail by a combination of SWBXT, transmission electron microscopy (TEM) and Raman spectroscopy to map defect types and distribution. X-ray diffraction analysis indicates the seed crystal contained stacking disorders and this appears to have been reproduced in the lateral growth sections. Analysis of the relative intensity for folded transverse acoustic (FTA) and optical (FTO) modes on the Raman spectra indicate the existence of stacking faults. Further, the density of stacking faults is higher in the seed than in the grown crystal. Bundles of dislocations are observed propagating from the seed in m-axis lateral directions. Contrast extinction analysis of these dislocation lines reveals they are edge type basal plane dislocations that track the growth direction. Polytype phase transition and stacking faults were observed by high-resolution TEM (HRTEM), in agreement with SWBXT and Raman scattering.

Single Crystal↗
NASA NTRS2013

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Chen, Liang-Yu↗
NASA NTRS2013

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Electronic packaging↗
NASA NTRS2012

A New Method to Grow SiC: Solvent-Laser Heated Floating Zone

The solvent-laser heated floating zone (solvent-LHFZ) growth method is being developed to grow long single crystal SiC fibers. The technique combines the single crystal fiber growth ability of laser heated floating zone with solvent based growth techniques (e.g. traveling solvent method) ability to grow SiC from the liquid phase. Initial investigations reported in this paper show that the solvent-LHFZ method readily grows single crystal SiC (retains polytype and orientation), but has a significant amount of inhomogeneous strain and solvent rich inclusions.

Woodworth, Andrew A.↗
NASA NTRS2012

A New Method to Grow SiC: Solvent-Laser Heated Floating Zone

The solvent-laser heated floating zone (solvent-LHFZ) growth method is being developed to grow long single crystal SiC fibers. The technique combines the single crystal fiber growth ability of laser heated floating zone with solvent based growth techniques (e.g. traveling solvent method) ability to grow SiC from the liquid phase. Initial investigations reported in this paper show that the solvent-LHFZ method readily grows single crystal SiC (retains polytype and orientation), but has a significant amount of inhomogeneous strain and solvent rich inclusions.

Woodworth, A. A.↗
NASA NTRS2011

High Temperature Capacitive Pressure Sensor Employing a SiC Based Ring Oscillator

In an effort to develop harsh environment electronic and sensor technologies for aircraft engine safety and monitoring, we have used capacitive-based pressure sensors to shift the frequency of a SiC-electronics-based oscillator to produce a pressure-indicating signal that can be readily transmitted, e.g. wirelessly, to a receiver located in a more benign environment. Our efforts target 500 C, a temperature well above normal operating conditions of commercial circuits but within areas of interest in aerospace engines, deep mining applications and for future missions to the Venus atmosphere. This paper reports for the first time a ring oscillator circuit integrated with a capacitive pressure sensor, both operating at 500 C. This demonstration represents a significant step towards a wireless pressure sensor that can operate at 500 C and confirms the viability of 500 C electronic sensor systems.

Meredith, Roger D.↗
NASA NTRS2011

Lateral Growth Expansion of 4H/6H-SiC m-plane Pseudo Fiber Crystals by Hot Wall CVD Epitaxy

Lateral expansion of small mixed polytype 4H/6H-SiC slivers were realized by hot wall chemical vapor deposition (HWCVD). Small slivers cut from m-oriented ..11..00.. SiC boule slices containing regions of 4H and 6H SiC were exposed to HWCVD conditions using standard silane/propane chemistry for a period of up to eight hours. The slivers exhibited approximately 1500 microns (1.5 mm) of total lateral expansion. Initial analysis by synchrotron white beam x-ray topography (SWBXT) confirms, that the lateral growth was homoepitaxial, matching the polytype of the respective underlying region of the seed sliver.

Trunek, Andrew J.↗
NASA NTRS2011

SiC growth by Solvent-Laser Heated Floating Zone

In an effort to grow single crystal SiC fibers for seed crystals the following two growth methods have been coupled in this work: traveling solvent and laser heated floating zone to create the solvent-laser heated floating zone (Solvent-LHFZ) crystal growth method. This paper discusses the results of these initial experiments, which includes: source material, laser heating, and analysis of the first ever Solvent-LHFZ SiC crystals (synchrotron white beam x-ray topography confirmed).

Woodworth, Andrew A.↗
NASA NTRS2011

Method for Providing Semiconductors Having Self-Aligned Ion Implant

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Neudeck, Philip G.↗
NASA NTRS2010

Low Earth Orbit Space Environment Testing of Extreme Temperature 6H-SiC JFETs on the International Space Station

This paper reports long-term electrical results from two 6H-SiC junction field effect transistors (JFETs) presently being tested in Low Earth Orbit (LEO) space environment on the outside of the International Space Station (ISS). The JFETs have demonstrated excellent functionality and stability through 4600 hours of LEO space deployment. Observed changes in measured device characteristics tracked changes in measured temperature, consistent with wellknown JFET temperature-dependent device physics.

Neudeck, Philip G.↗
NASA NTRS2009

Characterization of 6H-SiC JFET Integrated Circuits Over A Broad Temperature Range from -150 C to +500 C

The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 C to +500 C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.

Neudeck, Philip G.↗
NASA NTRS2009

Observations of Screw Dislocation Driven Growth and Faceting During CVD Homoepitaxy on 4H-SiC On-Axis Mesa Arrays

Previous studies of (0001) homoepitaxial growth carried out on arrays of small-area mesas etched into on-axis silicon-face 4H-SiC wafers have demonstrated that spiral growth emanating from at least one screw dislocation threading the mesa is necessary in order for a mesa to grow taller in the <0001> (c-axis vertical) direction while maintaining 4H stacking sequence [1]. However, even amongst mesas containing the screw dislocation step source necessary for vertical c-axis growth, we have observed striking differences in the height and faceting that evolve during prolonged homoepitaxial growths. This paper summarizes Atomic Force Microscopy (AFM), Electron Channeling Contrast Imaging (ECCI), Scanning Electron Microscopy (SEM), and optical microscopy observations of this phenomenon. These observations support our initially proposed model [2] that the observed large variation (for mesas where 3C-SiC nucleation has not occurred) is related to the lateral positioning of a screw dislocation step source within each etched mesa. When the screw dislocation step source is located close enough to the developing edge/sidewall facet of a mesa, the c-axis growth rate and facet angle are affected by the resulting interaction. In particular, the intersection (or near intersection) of the inward-sloping mesa sidewall facet with the screw dislocation appears to impede the rate at which the spiral provides new steps required for c-axis growth. Also, the inward slope of the sidewall facet during growth (relative to other sidewalls of the same mesa not near the screw dislocation) seems to be impeded by the screw dislocation. In contrast, mesas whose screw dislocations are centrally located grow vertically, but inward sloping sidewall facets shrink the area of the top (0001) growth surface almost to the point of vanishing.

Neudeck, Philip G.↗
NASA NTRS2008

SiC JFET Transistor Circuit Model for Extreme Temperature Range

A technique for simulating extreme-temperature operation of integrated circuits that incorporate silicon carbide (SiC) junction field-effect transistors (JFETs) has been developed. The technique involves modification of NGSPICE, which is an open-source version of the popular Simulation Program with Integrated Circuit Emphasis (SPICE) general-purpose analog-integrated-circuit-simulating software. NGSPICE in its unmodified form is used for simulating and designing circuits made from silicon-based transistors that operate at or near room temperature. Two rapid modifications of NGSPICE source code enable SiC JFETs to be simulated to 500 C using the well-known Level 1 model for silicon metal oxide semiconductor field-effect transistors (MOSFETs). First, the default value of the MOSFET surface potential must be changed. In the unmodified source code, this parameter has a value of 0.6, which corresponds to slightly more than half the bandgap of silicon. In NGSPICE modified to simulate SiC JFETs, this parameter is changed to a value of 1.6, corresponding to slightly more than half the bandgap of SiC. The second modification consists of changing the temperature dependence of MOSFET transconductance and saturation parameters. The unmodified NGSPICE source code implements a T(sup -1.5) temperature dependence for these parameters. In order to mimic the temperature behavior of experimental SiC JFETs, a T(sup -1.3) temperature dependence must be implemented in the NGSPICE source code. Following these two simple modifications, the Level 1 MOSFET model of the NGSPICE circuit simulation program reasonably approximates the measured high-temperature behavior of experimental SiC JFETs properly operated with zero or reverse bias applied to the gate terminal. Modification of additional silicon parameters in the NGSPICE source code was not necessary to model experimental SiC JFET current-voltage performance across the entire temperature range from 25 to 500 C.

Neudeck, Philip G.↗
NASA NTRS2008

Method for the growth of large low-defect single crystals

A method and the benefits resulting from the product thereof are disclosed for the growth of large, low-defect single-crystals of tetrahedrally-bonded crystal materials. The process utilizes a uniquely designed crystal shape whereby the direction of rapid growth is parallel to a preferred crystal direction. By establishing several regions of growth, a large single crystal that is largely defect-free can be grown at high growth rates. This process is particularly suitable for producing products for wide-bandgap semiconductors, such as SiC, GaN, AlN, and diamond. Large low-defect single crystals of these semiconductors enable greatly enhanced performance and reliability for applications involving high power, high voltage, and/or high temperature operating conditions.

Powell, J. Anthony↗