Engineering topics
Publications and source records attributed to Ipri, A. C..
Report discusses set of design rules that have been developed as result of work with test arrays. Set of optimum dimensions is given that would maximize process output and would correspondingly minimize costs in fabrication of large-scale integration (LSI) arrays.
A technique is described for determining the applicability of a particular process for the fabrication of large-scale integrated (LSI) circuits. Test arrays were developed to isolate various critical processing steps in a fabrication sequence and a statistical evaluation of these steps was carried out that related yield or success in achieving a desired result to the number of times the results were attempted. It was found that, in general, yield is a sensitive function of physical dimensions as is the packing density of a particular array. It is, therefore, possible to generate an optimum set of physical dimensions or design rules that maximize the expected number of working circuits on a wafer.
The applicability of a particular process for the fabrication of large scale integrated circuits is described. Test arrays were designed, built, and tested, and then utilized. A set of optimum dimensions for LSI arrays was generated. The arrays were applied to yield improvement through process innovation, and additional applications were suggested in the areas of yield prediction, yield modeling, and process reliability.
The work on the Process Analysis Structure was continued with the layout being completed, the 100X and 10X artwork being finalized, and the process and test sequences being prepared. Test programs were written for computer-controlled integrated-circuit testing and data reduction.
The Si-gate CMOS/SOS process used to manufacture integrated circuits is examined. A process analysis test structure is developed to determine the defect mechanisms most detrimental to yield, control, and reliability.