Engineering topics
Guertin, Steven M.
Publications and source records attributed to Guertin, Steven M..
Radiation specification and testing of heterogenous microprocessor SOCs
Modern commercial microprocessor devices include multiple processor architectures, buses, basic peripherals, and application hardware such as Graphics Processing Units (GPUs) and Digital Signal Processors (DSPs) in one device. Developing RHBD versions of similar devices risks sacrificing processing performance for system-wide radiation requirements. The heterogenous structure of modern commercial system on a chip (SOC) devices, in design and performance goals for subsystems, suggests a similar approach to specifying Radiation Hardened by Design (RHBD) requirements.
Evaluating Elevated Temperature DRAM Stuck Bit Sensitivity at Room Temperature
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Proton Board-Level Testing: Achieving Limited Radiation Assurance with Minimal Testing
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Lessons and Recommendations for Board-Level Testing with Protons
Protons with sufficiently high energy, provided in a broad field covering on the order of 0.1m2 can be used to perform board-level testing for single event effects (SEE). NASA has used this approach for board-level testing over the last 20 years. Although many difficulties inherent in SEE testing are simplified when using a board-level test, including reduced cost, the method is inherently risky because of the limited value of the collected data and the potential to make critical mistakes when performing SEE testing this way, leading to data of less value. Historically, NASA’s approach to proton board-level testing has been limited to lower criticality applications. However, with users both inside and outside NASA using this method for higher levels of mission assurance, we have put together a set of lessons and recommendations to improve the value of data collected using this method. Focus areas covered include test preparation, test execution, and interpretation of results.
Radiation Performance of Memory Technologies for Space Applications
MRAM and DRAM memory technologies identified for possible radiation hardening were investigated for memory-array- and controller-level radiation sensitivity. TID and SEE performance of memory arrays and associated cells is good, but with some questions about viability of hardening of problematic control circuitry. Control-circuitry-related SEE problems are highlighted. TID data are focused on memory arrays only.
Guideline for Single-Event Effect (SEE) Testing of System on a Chip (SOC) Devices
The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.
Board Level Proton Testing Book of Knowledge for NASA Electronic Parts and Packaging Program
This book of knowledge (BoK) provides a critical review of the benefits and difficulties associated with using proton irradiation as a means of exploring the radiation hardness of commercial-off-the-shelf (COTS) systems. This work was developed for the NASA Electronic Parts and Packaging (NEPP) Board Level Testing for the COTS task. The fundamental findings of this BoK are the following. The board-level test method can reduce the worst case estimate for a board's single-event effect (SEE) sensitivity compared to the case of no test data, but only by a factor of ten. The estimated worst case rate of failure for untested boards is about 0.1 SEE/board-day. By employing the use of protons with energies near or above 200 MeV, this rate can be safely reduced to 0.01 SEE/board-day, with only those SEEs with deep charge collection mechanisms rising this high. For general SEEs, such as static random-access memory (SRAM) upsets, single-event transients (SETs), single-event gate ruptures (SEGRs), and similar cases where the relevant charge collection depth is less than 10 μm, the worst case rate for SEE is below 0.001 SEE/board-day. Note that these bounds assume that no SEEs are observed during testing. When SEEs are observed during testing, the board-level test method can establish a reliable event rate in some orbits, though all established rates will be at or above 0.001 SEE/board-day. The board-level test approach we explore has picked up support as a radiation hardness assurance technique over the last twenty years. The approach originally was used to provide a very limited verification of the suitability of low cost assemblies to be used in the very benign environment of the International Space Station (ISS), in limited reliability applications. Recently the method has been gaining popularity as a way to establish a minimum level of SEE performance of systems that require somewhat higher reliability performance than previous applications. This sort of application of the method suggests a critical analysis of the method is in order. This is also of current consideration because the primary facility used for this type of work, the Indiana University Cyclotron Facility (IUCF) (also known as the Integrated Science and Technology (ISAT) hall), has closed permanently, and the future selection of alternate test facilities is critically important. This document reviews the main theoretical work on proton testing of assemblies over the last twenty years. It augments this with review of reported data generated from the method and other data that applies to the limitations of the proton board-level test approach. When protons are incident on a system for test they can produce spallation reactions. From these reactions, secondary particles with linear energy transfers (LETs) significantly higher than the incident protons can be produced. These secondary particles, together with the protons, can simulate a subset of the space environment for particles capable of inducing single event effects (SEEs). The proton board-level test approach has been used to bound SEE rates, establishing a maximum possible SEE rate that a test article may exhibit in space. This bound is not particularly useful in many cases because the bound is quite loose. We discuss the established limit that the proton board-level test approach leaves us with. The remaining possible SEE rates may be as high as one per ten years for most devices. The situation is actually more problematic for many SEE types with deep charge collection. In cases with these SEEs, the limits set by the proton board-level test can be on the order of one per 100 days. Because of the limited nature of the bounds established by proton testing alone, it is possible that tested devices will have actual SEE sensitivity that is very low (e.g., fewer than one event in 1 × 10(exp 4) years), but the test method will only be able to establish the limits indicated above. This BoK further examines other benefits of proton board-level testing besides hardness assurance. The primary alternate use is the injection of errors. Error injection, or fault injection, is something that is often done in a simulation environment. But the proton beam has the benefit of injecting the majority of actual SEEs without risk of something being missed, and without the risk of simulation artifacts misleading the SEE investigation.
Compendium of Current Single Event Effects Results from NASA Goddard Space Flight Center and NASA Electronic Parts and Packaging Program
We present the results of single event effects (SEE) testing and analysis investigating the effects of radiation on electronics. This paper is a summary of test results.