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Ghaffarian, Reza

Publications and source records attributed to Ghaffarian, Reza.

54 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

CHEM-Based Self-Deploying Spacecraft Radar Antennas

A document proposes self-deploying spacecraft radar antennas based on cold hibernated elastic memory (CHEM) structures. Described in a number of prior NASA Tech Briefs articles, the CHEM concept is one of utilizing open-cell shape-memory-polymer (SMP) foams to make lightweight structures that can be compressed for storage and can later be expanded, then rigidified for use. A CHEM-based antenna according to the proposal would comprise three layers of microstrip patches and transmission lines interspersed with two flat layers of SMP foam, which would serve as both dielectric spacers and as means of deployment. The SMP foam layers would be fabricated at full size at a temperature below the SMP glass-transition temperature (Tg). The layers would be assembled into a unitary structure, which, at temperature above Tg, would be compacted to much smaller thickness, then rolled up for storage. Next, the structure would be cooled to below Tg and kept there during launch. Upon reaching the assigned position in outer space, the structure would be heated above Tg to make it rebound to its original size and shape. The structure as thus deployed would then be rigidified by natural cooling to below Tg

Sokolowski, Witold↗
NASA NTRS2004

Qualification and Reliability for MEMS and IC Packages

Advanced IC electronic packages are moving toward miniaturization from two key different approaches, front and back-end processes, each with their own challenges. Successful use of more of the back-end process front-end, e.g. microelectromechanical systems (MEMS) Wafer Level Package (WLP), enable reducing size and cost. Use of direct flip chip die is the most efficient approach if and when the issues of know good die and board/assembly are resolved. Wafer level package solve the issue of known good die by enabling package test, but it has its own limitation, e.g., the I/O limitation, additional cost, and reliability. From the back-end approach, system-in-a-package (SIAP/SIP) development is a response to an increasing demand for package and die integration of different functions into one unit to reduce size and cost and improve functionality. MEMS add another challenging dimension to electronic packaging since they include moving mechanical elements. Conventional qualification and reliability need to be modified and expanded in most cases in order to detect new unknown failures. This paper will review four standards that already released or being developed that specifically address the issues on qualification and reliability of assembled packages. Exposures to thermal cycles, monotonic bend test, mechanical shock and drop are covered in these specifications. Finally, mechanical and thermal cycle qualification data generated for MEMS accelerometer will be presented. The MEMS was an element of an inertial measurement unit (IMU) qualified for NASA Mars Exploration Rovers (MERs), Spirit and Opportunity that successfully is currently roaring the Martian surface

inertial measurement unit↗
NASA NTRS2002

Low Temperature Reliability of Electronic Packages/Assemblies for Space Missions

A NASA-wide team, funded under the NASA Electronic Parts and Packaging Program (NEPP), was formed to collaborate and to establish reliability of various electronic parts/packaging and assemblies for operation under extreme cold temperatures. One of the primary objectives of the NEPP is to expedite the infusion of cutting edge technologies into the present and future NASA missions. Commercial-off-the-shelf (COTS) emerging electronic parts/packages due to their lower weight, increased functionality, and lower cost are excellent candidates for space missions if they are characterized to show that they will meet the stringent reliability and quality requirements. Characterizations, especially for the extreme cold temperatures, are required since very limited data are available by manufacturers or users. For severe military environments, the temperature conditions to -65 C are the lowest temperature for which these parts/packages and assemblies are qualified. New data beyond this relatively benign cold temperature are required for numerous NASA missions. Several parts/packages, based on the project recommendation for their immediate and future needs, were selected for detailed characterization to cold temperature regimes down to liquid nitrogen (-196 C), covering both Mars cold temperature (-125 C) and asteroid (- 180 C) lander environmental requirements. Numerous parts/packages and assemblies were characterized during extreme temperature environmental tests. Several electrical parameters were characterized at discrete temperatures to -185 C to determine if they remain within their specification ranges. Both packages and circuit boards were subjected to nondestructive testing including optical, X-ray, and acoustic microscopy to document their integrity prior to environment exposure. Package/board assemblies were also subjected to X-ray to characterize solder joint integrity including void levels. Both parts and assemblies were subjected to thermal cycling with a large temperature swing enveloping numerous NASA missions. Details of the performed tests and the results obtained are presented.

Patterson, Richard L.↗
NASA NTRS2001

Low Temperature Testing of a Radiation Hardened CMOS 8-Bit Flash Analog-to-Digital (A/D) Converter

Power processing electronic systems, data acquiring probes, and signal conditioning circuits are required to operate reliably under harsh environments in many of NASA:s missions. The environment of the space mission as well as the operational requirements of some of the electronic systems, such as infrared-based satellite or telescopic observation stations where cryogenics are involved, dictate the utilization of electronics that can operate efficiently and reliably at low temperatures. In this work, radiation-hard CMOS 8-bit flash A/D converters were characterized in terms of voltage conversion and offset in the temperature range of +25 to -190 C. Static and dynamic supply currents, ladder resistance, and gain and offset errors were also obtained in the temperature range of +125 to -190 C. The effect of thermal cycling on these properties for a total of ten cycles between +80 and - 150 C was also determined. The experimental procedure along with the data obtained are reported and discussed in this paper.

Gerber, Scott S.↗
NASA NTRS2000

Accelerated Thermal Cycling and Failure Mechanisms for BGA and CSP Assemblies

This paper reviews the accelerated thermal cycling test methods that are currently used by industry to characterize the interconnect reliability of commercial-off-the-shelf (COTS) ball grid array (BGA) and chip scale package (CSP) assemblies. Acceleration induced failure mechanisms varied from conventional surface mount (SM) failures for CSPs. Examples of unrealistic life projections for other CSPs are also presented. The cumulative cycles to failure for ceramic BGA assemblies performed under different conditions, including plots of their two Weibull parameters, are presented. The results are for cycles in the range of -30 C to 100 C, -55 C to 100 C, and -55 C to 125 C. Failure mechanisms as well as cycles to failure for thermal shock and thermal cycling conditions in the range of -55 C to 125 C were compared. Projection to other temperature cycling ranges using a modified Coffin-Manson relationship is also presented.

Ghaffarian, Reza↗
NASA NTRS2000

CSP Manufacturing Challenges and Assembly Reliability

Although the expression of CSP is widely used by industry from suppliers to users, its implied definition had evolved as the technology has matured. There are "expert definition"- package that is up to 1.5 time die- or "interim definition". CSPs are miniature new packages that industry is starting to implement and there are many unresolved technical issues associated with their implementation. For example, in early 1997, packages with 1 mm pitch and lower were the dominant CSPs, whereas in early 1998 packages with 0.8 mm and lower became the norm for CSPs. Other changes included the use of flip chip die rather than wire bond in CSP. Nonetheless the emerging CSPs are competing with bare die assemblies and are becoming the package of choice for size reduction applications. These packages provide the benefits of small size and performance of the bare die or flip chip, with the advantage of standard die packages. The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. This talk will cover specifically the experience of our consortium on technology implementation challenges, including design and build of both standard and microvia boards, assembly of two types of test vehicles, and the most current environmental thermal cycling test results.

Ghaffarian, Reza↗
NASA NTRS1998

Chip Scale Package Implementation Challenges

The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. In the process of building the Consortium CSP test vehicles, many challenges were identified regarding various aspects of technology implementation. This paper will present our experience in the areas of technology implementation challenges, including design and building both standard and microvia boards, and assembly of two types of test vehicles. We also discuss the most current package isothermal aging to 2,000 hours at 100 C and 125 C and thermal cycling test results to 1,700 cycles in the range of -30 to 100 C.

Ghaffarian, Reza↗
NASA NTRS1998

Chip Scale Package Integrity Assessment by Isothermal Aging

Many aspects of chip scale package (CSP) technology, with focus on assembly reliability characteristics, are being investigated by the JPL-led consortia. Three types of test vehicles were considered for evaluation and currently two configurations have been built to optimize attachment processes. These test vehicles use numerous package types. To understand potential failure mechanisms of the packages, particularly solder ball attachment, the grid CSPs were subjected to environmental exposure. Package I/Os ranged from 40 to nearly 300. This paper presents both as assembled, up to 1, 000 hours of isothermal aging shear test results and photo micrographs, and tensile test results before and after 1,500 cycles in the range of -30/100 C for CSPs. Results will be compared to BGAs with the same the same isothermal aging environmental exposures.

Ghaffarian, Reza↗
NASA NTRS1997

Ball Grid Array Reliability Assessment for Aerospace Applications

Reliability of Ball Grid Array(BGAs) was evaluated with special emphasis on space applications. This work was performed as part of a consortium led by the Jet Propulsion Laboratory (JPL) to help build the infrastructure necessary for implementation of this technology. Nearly 200 test vehicles, each with four packages, were assembled and tested using an experimental design.

Aerospace↗
NASA NTRS1997

A Review of Chip Scale Package Assembled Reliability

NASA Headquarters, code Q, has established the Advanced Interconnect Program (AIP) to address the NASA's Common needs in electronic packaging for microspacecraft applications. The Jet Propulsion Laboratory was funded to address the quality and reliability of several high denstiy electronic packaging technologies.

Chip Scale Packaging Microspacecraft↗
NASA NTRS1996

Area Array Technology Evaluations for Space and Military Applications

The Jet Propulsion Laboratory (JPL) is currently assessing the use of Area Array Packaging (AAP) for National Aeronautics and Space Administration (NASA) spaceflight applications. this work is being funded through NASA Headquarters, Code Q. The paper discusses background of AAP, objectives, and uses of AAP.

AAP Area Array Technology↗