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Ghaffarian, Reza

Publications and source records attributed to Ghaffarian, Reza.

At least 37 records · Page 2

BOK-Underfill Optimization for FPGA Package/Assembly

Commercial-off-the-shelf area array package technologies in high-reliability versions are being considered for NASA electronic systems. These packages are prone to early failure due to the severe mechanical shock and vibration of launch, as well as other less severe conditions, such as mechanical loading during descent, rough terrain mobility, handling, and ground tests. As the density of these packages increases and the size of ball interconnections decrease, susceptibility to mechanical loading and cycling fatigue grows. This report presents a summary of the body of knowledge developed for the evaluation of area array packages and is based on surveys of literature from industry and academia. For high-reliability applications, the limited data that exists will be presented. Most data from industry deals with mechanical fatigue caused by four-point bend tests, as well as from drop tests for hand-held electronics; the most recent data will be presented, along with a brief background of prior literature. Understanding the key design guidelines and failure mechanisms from past tests is critical to developing an approach that will minimize future failures. Additional specific testing enables low-risk insertion of these advanced electronic packages.

mechanical fatigue

Reliability of area array packages with 1500-2500 I/Os

This report first provides a literature survey for designing, manufacturing, and reliability test results for area array packages with 1500 to 2500 inputs/outputs (I/Os). It then presents test matrix on design, yield, and workmanship defects on assembly and environmental testing, including thermal cycle and mechanical drop-test evaluation results for FCBGA1704, FPBGA432, and PBGA676 I/Os packages assembled onto printed circuit/wiring boards (PCBs/PWBs). Finally, it summarizes lessons learned from test results for assembly and environmental testing along with optical, scanning electron microscopy (SEM), and x-ray photomicrographs showing damage progress.

Ghaffarian, Reza

Evaluation methodology guidance for stack packages

This report provides evaluation methodology guidance based on previous National Aeronautics and Space Administration (NASA) reports and literature surveys for 3D stack packages and assemblies. Two aspects of technology are covered: the package itself (guidance for functional packages) and package assembly manufacturing and reliability. This work was funded by the NASA Electronic Parts and Packaging (NEPP) Program. The objectives of this NEPP project are to: Perform a literature survey of 3D stack technology; perform a literature survey on the evaluation methodology for 3D package and assembly; combine the two aspects to provide evaluation methodology for both aspects with consideration of interactions between package and assembly; generate guidance on the evaluation methodology for 3D stack package integrity prior to and after assembly; provide recommendations on future experimental activities. The qualification and evaluation methodology guidelines will facilitate NASA projects in effectively evaluating the reliability of very dense and newly available high-density 3D stack packages, allowing more processing power in a smaller board footprint and lower system weight.

Gerke, David

Reliability of recolumned area array packages

This report presents qualification guidelines developed for recolumned, high I/O ceramic column grid array (CCGA) packages assembled onto printed wiring/circuit boards (PWBs/PCBs). It includes recolumn and assembly process development for two types of CCGA packages: those with and those without interposer. Thermal cycle test results and photomicrographs showing damage progress for recolumned CCGA assemblies are documented and presented.

Ghaffarian, Reza

Thermal Cycle Reliability and Failure Mechanisms of CCGA and PBGA Assemblies with and without Corner Staking

Area array packages (AAPs) with 1.27 mm pitch have been the packages of choice for commercial applications; they are now starting to be implemented for use in military and aerospace applications. Thermal cycling characteristics of plastic ball grid array (PBGA) and chip scale package assemblies, because of their wide usage for commercial applications, have been extensively reported on in literature. Thermal cycling represents the on-off environmental condition for most electronic products and therefore is a key factor that defines reliability.However, very limited data is available for thermal cycling behavior of ceramic packages commonly used for the aerospace applications. For high reliability applications, numerous AAPs are available with an identical design pattern both in ceramic and plastic packages. This paper compares assembly reliability of ceramic and plastic packages with the identical inputs/outputs(I/Os) and pattern. The ceramic package was in the form of ceramic column grid array (CCGA) with 560 I/Os peripheral array with the identical pad design as its plastic counterpart.

plastic ball grid array (PBGA)

Reliability of PWB Microvias for High Density Package Assembly

High density PWB (printed wiring board) with microvia technology is required for implementation of high density and high I/O area array packages (AAP). COTS (commercial off-the-shelf) AAP packaging technologies in high reliability versions with 1.27 mm pitch are now being considered for use in a number of NASA systems including Space Shuttle and Mars Rovers. NASA functional system designs are requiring more and more dense AAP packages and board space, which makes board microvia technology very attractive for effectively routing a large number of package inputs/outputs. However, the reliability of the fine feature microvias including via in pads is unknown for space applications. Understanding process and QA (quality assurance) indicators for reliability are important for low risk insertion of these newly available packages and PWBs. This paper presents literature search as well as test results for a high density board subjected to various thermal cycle and reflow profiles representative of tin-lead and lead-free solder reflow. Microvias sizes ranged from two to six mil with and without filling. Daisy chain microvias monitored during the test and PWBs were cross-sectioned to determine failure and locations. Optical and SEM photographs as well as resistance changes during cycling and Tg/Td (glass transition/decomposition temperature) characterisations are presented.

fill via

Thermal Cycle Reliability of PBGA/CCGA 717 I/Os

Status of thermal cycle test results for a nonfunctional daisy-chained peripheral ceramic column grid array (CCGA) and its plastic ball grid array (PBGA) version. both having 560 I/Os. were presented in last year's conference. Test results included environmental data for three different thermal cycle regimes (-55 C/125 C, -55 C/100 C, and -50 C /75 C). Update information on these - especially failure type for assemblies with high and low solder volumes-were presented. The thermal cycle test procedure followed those recommended IPC-9701 for tin-lead solder joint assemblies. Revision A of this specification covers guideline thermal cycle requirements for Pb-free solder joints. Some background information discussed during release of this specification with its current guideline recommendations were also presented. In a recent reliability investigation a fully populated CCGA with 717 I/Os was also considered for assembly reliability. evaluation. The functional package is a field-programmable gate array that has much higher processing power than its previous version. This new package is smaller in dimension, has no interposer, and has a thinner column wrapped with copper for reliability improvement. This paper will also present thermal cycle test results for this package assembly and its plastic version with 728 I/Os. both of which were exposed to three different cycle regimes. Two cycle profiles were those specified by IPC- 9701A for tin-lead, i.e. -55 to 100 C and -55 to 125 C and one was a cycle profile specified by Mil-Std-883, i.e.. -65 C/150 C which is generally used for ceramic hybrid packages. Per IPC-9701 A, test vehicles were built using daisy chain packages and were continuously monitored. The effects of many process and assembly variables-including corner staking commonly used for improving resistance to mechanical loading such as drop and vibration loads--were also considered as part of the test matrix. Optical photomicrographs were taken at various thermal cycle intervals to document damage progress and behavior. Representative samples of these along with cross-sectional photomicrographs at higher magnification taken by scanning electron microscopy (SEM) to determine crack propagation and failure analyses for packages are also presented.

staking

Surface Control of Cold Hibernated Elastic Memory Self-Deployable Structure

A new class of simple, reliable, lightweight, low packaging volume and cost, self-deployable structures has been developed for use in space and commercial applications. This technology called 'cold hibernated elastic memory' (CHEM) utilizes shape memory polymers (SMP)in open cellular (foam) structure or sandwich structures made of shape memory polymer foam cores and polymeric composite skins. Some of many potential CHEM space applications require a high precision deployment and surface accuracy during operation. However, a CHEM structure could be slightly distorted by the thermo-mechanical processing as well as by thermal space environment Therefore, the sensor system is desirable to monitor and correct the potential surface imperfection. During these studies, the surface control of CHEM smart structures was demonstrated using a Macro-Fiber Composite (MFC) actuator developed by the NASA LaRC and US Army ARL. The test results indicate that the MFC actuator performed well before and after processing cycles. It reduced some residue compressive strain that in turn corrected very small shape distortion after each processing cycle. The integrated precision strain gages were detecting only a small flat shape imperfection indicating a good recoverability of original shape of the CHEM test structure.

glass transition temperature Tg

Design Parameters Influencing Reliability of CCGA Assembly: A Sensitivity Analysis

Area Array microelectronic packages with small pitch and large I/O counts are now widely used in microelectronics packaging. The impact of various package design and materials/process parameters on reliability has been studied through extensive literature review. Reliability of Ceramic Column Grid Array (CCGA) package assemblies has been evaluated using JPL thermal cycle test results (-50(deg)/75(deg)C, -55(deg)/100(deg)C, and -55(deg)/125(deg)C), as well as those reported by other investigators. A sensitivity analysis has been performed using the literature da to study the impact of design parameters and global/local stress conditions on assembly reliability. The applicability of various life-prediction models for CCGA design has been investigated by comparing model's predictions with the experimental thermal cycling data. Finite Element Method (FEM) analysis has been conducted to assess the state of the stress/strain in CCGA assembly under different thermal cycling, and to explain the different failure modes and locations observed in JPL test assemblies.

reliability

Lead-Free vs Tin-Lead Reliability of Advanced Electronic Assemblies

This presentation will provide the technical background and specific information published in literature related to reliability test, analyses, modeling, and associated issues for lead-free solder package assemblies in comparison to their tin-lead solder alloys. It also presents current understanding of lead-free thermal cycle test performance in support.

assembly reliability

Reliability of CCGA and PBGA assemblies

Area Array Packages (AAPs) with 1.27 mm pitch have been the packages of the choice for commercial applications; they are now started to be implemented for use in military and aerospace applications. Thermal cycling characteristics of plastic BGA (PBGA) and CSP assemblies, because of their wide usage for commercial applications, have been extensively reported in literature. Thermal cycling represents the on-off environmental condition for most electronic products and therefore is a key factor that defines reliability.

stakes

Reliability Assessment of Advanced Flip-clip Interconnect Electronic Package Assemblies under Extreme Cold Temperatures (-190 and -120 C)

Flip-chip interconnect electronic package boards have been assembled, underfilled, non-destructively evaluated and subsequently subjected to extreme temperature thermal cycling to assess the reliability of this advanced packaging interconnect technology for future deep space, long-term, extreme temperature missions. In this very preliminary study, the employed temperature range covers military specifications (-55 C to 100 C), extreme cold Martian (-120 C to 115 C) and asteroid Nereus (-180 C to 25 C) environments. The resistance of daisy-chained, flip-chip interconnects were measured at room temperature and at various intervals as a function of extreme temperature thermal cycling. Electrical resistance measurements are reported and the tests to date have not shown significant change in resistance as a function of extreme temperature thermal cycling. However, the change in interconnect resistance becomes more noticeable with increasing number of thermal cycles. Further research work has been carried out to understand the reliability of flip-chip interconnect packages under extreme temperature applications (-190 C to 85 C) via continuously monitoring the daisy chain resistance. Adaptation of suitable diagnostic techniques to identify the failure mechanisms is in progress. This presentation will describe the experimental test results of flip-chip testing under extreme temperatures.

thermal cycling

Lead free 0201 assembly and thermal cycle/aging reliability

The many challenges with 0201 passive component assembly can be attributed to the solder paste volume, pad design, aperture design, board finish, type of solder paste, pick-and-place, and reflow profile. A Design-of-Experiment (DOE) study was carried out to investigate the effects of these parameters on assembly defects and reliability.

isothermal aging