Engineering topics
Publications and source records attributed to Feltner, W. R..
Radiative temperature regulators have no moving parts. Conceptual temperature-regulating system proposed for spacecraft useful in automatic or remotely controlled regulation of solar heating in buildings, provided cost reduced sufficiently. System consists of liquid-crystal panels made to absorb or reflect sunlight.
Method of removing positive ions from oxides in metal-oxide-semiconductor (MOS) transistors and intergrated circuits ensure freedom from contamination by sodium and other mobile positive ions. Electric field applied during oxide growth to push mobile Na + ions to surface. After cooling from growth temperature, field turned off and Na + contaminated surface layer etched away. New method intended to suplement established methods of minimizing ion contamination, such as scrupulous cleanliness in processing, purging with hydrogen chloride to react with and remove contaminants, and growing extra-thick gate oxide, then etching it to remove large portion of contaminants concentrated near surface.
Modified ion-bombardment technqiue interconnects MOS circuit elements without affecting circuit parameters. Multilevel metalization involves: surface treatment prior to metalization; first metalization; metal pattern definition and photoresist removal; dielectric deposition; second metalization; and final dielectric deposition.
The fabrication techniques for creation of complementary metal oxide semiconductor integrated circuits at George C. Marshall Space Flight Center are described. Examples of C-MOS integrated circuits manufactured at MSFC are presented with functional descriptions of each. Typical electrical characteristics of both p-channel metal oxide semiconductor and n-channel metal oxide semiconductor discrete devices under given conditions are provided. Procedures design, mask making, packaging, and testing are included.
Report describes complementary metal-oxide-semiconductor (CMOS) process used to fabricate integrated circuits at Marshall Space Flight Center. It also presents general discussions of circuit design, mask making packaging, and testing.
The method of constructing a high voltage, low power, multicell solar array is described. A solar cell base region is formed in a substrate such as but not limited to silicon or sapphire. A protective coating is applied on the base and a patterned etching of the coating and base forms discrete base regions. A semiconductive junction and upper active region are formed in each base region, and defined by photolithography. Thus, discrete cells which are interconnected by metallic electrodes are formed.
An improved method is described of constructing a metal oxide semiconductor device having multiple layers of metal deposited by dc magnetron sputtering at low dc voltages and low substrate temperatures. The method provides multilevel interconnections and cross over between individual circuit elements in integrated circuits without significantly reducing the reliability or seriously affecting the yield.
Technique increases switching speeds, shortens channel length, reduces parasitic capacitance and gate overlap, and minimizes gate-to-channel capacitance. The p and n sections may be reversed, allowing fabrication of complementary devices.
The fabrication techniques and detail procedures for creating P-channel Metal-Oxide-Semiconductor (P-MOS) integrated circuits at George C. Marshall Space Flight Center (MSFC) are described. Examples of P-MOS integrated circuits fabricated at MSFC together with functional descriptions of each are given. Typical electrical characteristics of high and low threshold P-MOS discrete devices under given conditions are provided. A general description of MSFC design, mask making, packaging, and testing procedures is included. The capabilities described in this report are being utilized in: (1) research and development of new technology, (2) education of individuals in the various disciplines and technologies of the field of microelectronics, and (3) fabrication of many types of specially designed integrated circuits which are not commercially feasible in small quantities for in-house research and development programs.