Fully Parallel ASIC Interface for a 3 Dimensional Processor for Image Convolution
Explore the source record for details and available documents.
CLIC die NPM cube fabricated die-jig digital circu↗
Engineering topics
Daud, T.
Publications and source records attributed to Daud, T..
Room and Low Temperature Performance of High-Speed Neural Network Circuits
We have described a challenging neural-network hardware implementation that would mate a 64x64-pixel infrared sensor directly on to a 3-dimensionally packaged set of neural processing chips with parallel input for high speed image processing. Non linearity effects and range compression are also discussed.
high-speed neural network circuits neural network ↗
VIGILANTE: An Advanced Sensing/Processing Testbed for ATR Applications
VIGILANTE consists of two major components:1. the Viewing Imager/Gimballed Instrumentation Laboratory (VIGIL)- advanced infrared, visible, and ultraviolet sensors with appropriate optics and camera electronics & 2. the Analog Neural Three-dimensional processing Experiment (ANTE)-a massively parallel, neural network-based, high-speed processor.
automatic↗
64x64 Analog Input Array for 3-Dimensional Neural Network Processor
In pattern recognition and classification for spatio-temporal problems, one of the most challenging tasks is to provide a good and valid solution in real-time. Because of time constraints, software-based neural network approaches may not be suitable for practical use. Hardware solutions seem to be good candidates for this class of problems. Currently, the Three Dimensional Analog Neural Network (3-DANN) is an effective approach to solving spatio-temporal problems in three-dimensional hardware.
spatio-temporal 3-DANN Three Dimensional Analog Ne↗
Radiation Behavior of Analog Neural Network Chip
A neural network experiment conducted for the Space Technology Research Vehicle (STRV-1) 1-b launched in June 1994. Identical sets of analog feed-forward neural network chips was used to study and compare the effects of space and ground radiation on the chips. Three failure mechanisms are noted.
neural networks radiation hardening graceful degra↗
Cascade Error Projection: A New Learning Algorithm
A new neural network architecture and a hardware implementable learning algorithm is proposed. The algorithm, called cascade error projection (CEP), handles lack of precision and circuit noise better than existing algorithms.
neural network learning algorithm cascade error pr↗
Low Temperature Performance of High-Speed Neural Network Circuits
Artificial neural networks, derived from their biological counterparts, offer a new and enabling computing paradigm specially suitable for such tasks as image and signal processing with feature classification/object recognition, global optimization, and adaptive control. When implemented in fully parallel electronic hardware, it offers orders of magnitude speed advantage. Basic building blocks of the new architecture are the processing elements called neurons implemented as nonlinear operational amplifiers with sigmoidal transfer function, interconnected through weighted connections called synapses implemented using circuitry for weight storage and multiply functions either in an analog, digital, or hybrid scheme.
artificial neural networks image processing signal↗
Cascade Error Projection Learning Algorithm
A detailed mathematical analysis is presented for a new learning algorithm termed cascade error projection (CEP) and a general learning frame work. This frame work can be used to obtain the cascade correlation learning algorithm by choosing a particular set of parameters.
learning algorithm neural network cascade error pr↗
Mine Discrimination Using Multispectral Imagery With Feedforward Neural Networks
Simulated mine detection was performed on a polarimetric hyperspectral imaging dataset collected by using an acousto-optic tunable filter camera. A feedforward artificial neural network was programmed to recognize predefined spectral "templates." The simulation results are provided along with the preprocessing steps and window sizes leading to mine detection without false alarms.
polarimetric↗
Low Power Analog Neurosynapse Chips for a 3-D 'Sugarcube' Neuroprocessor
Object discrimination and patttern recognition are computationally intensive and for many defense and commercial applications, speed is of the essence.
3-D VLSI architecture reconfigurable multilayer pe↗
Learning to Classify Map Data with Cascaded VLSI Neural Network Building Block Chips
Paper maps are an important but unwieldy data format. To increase its utility, copious amounts of map data have been scanned into a digital map knowledge base. The next task in this knowledge base is to reduce this data to its underlying feature form suitable for analysis.
VLSI Neural Network Map Data↗
Learning and optimization with cascaded VLSI neural network building-block chips
To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.
Duong, T.↗
Electronic neural network for dynamic resource allocation
A VLSI implementable neural network architecture for dynamic assignment is presented. The resource allocation problems involve assigning members of one set (e.g. resources) to those of another (e.g. consumers) such that the global 'cost' of the associations is minimized. The network consists of a matrix of sigmoidal processing elements (neurons), where the rows of the matrix represent resources and columns represent consumers. Unlike previous neural implementations, however, association costs are applied directly to the neurons, reducing connectivity of the network to VLSI-compatible 0 (number of neurons). Each row (and column) has an additional neuron associated with it to independently oversee activations of all the neurons in each row (and each column), providing a programmable 'k-winner-take-all' function. This function simultaneously enforces blocking (excitatory/inhibitory) constraints during convergence to control the number of active elements in each row and column within desired boundary conditions. Simulations show that the network, when implemented in fully parallel VLSI hardware, offers optimal (or near-optimal) solutions within only a fraction of a millisecond, for problems up to 128 resources and 128 consumers, orders of magnitude faster than conventional computing or heuristic search methods.
Thakoor, A. P.↗
Competitive neural architecture for hardware solution to the assignment problem
The architecture for competitive assignment is described with attention given to the VLSI design and critical circuits fabricated in complementary metal-oxide semiconductor. The local application of association costs to processing units reduces the connectivity to the number of VLSI-compatible processing units. 'Hysteretic annealing' is discussed and when compared to mean-field annealing is found to enhance processing-unit gain and provide near-optimal solutions in about 150 microsec.
Eberhardt, S. P.↗
Solid-state reprogrammable analog resistive devices for electronic neural networks
The fabrication and performance of WO3-based, solid-state, three-terminal device configurations as programmable analog memory elements are reported. These transistorlike device structures exhibit good resistance progammability with a remarkable resolution of a few percent of the resistive strength over a four orders of magnitude dynamic range. The most critical component of these devices is an insulating layer between the active WO3 and the cation donor layer. The progamming characteristics and operation mechanisms of the device are described, and probable reaction mechanisms critical to the device stability are discussed.
Ramesham, R.↗
Solid-state thin-film memistor for electronic neural networks
This paper reports on a tungsten-oxide-based, nonvolatile, electrically reprogrammable, variable resistance device as an analog synaptic memory connection for electronic neural networks. A voltage controlled, reversible injection of H(+) ions in electrochromic thin films of WO3 is utilized to modulate its resistance. A hygroscopic thin film of Cr2O3 is the source of H(+) ions. The resistance of the device can be tailored and stabilized over a wide dynamic range (about 4 orders of magnitude), and the programming speed is modulated by the control voltage. The suitability of such a device in terms of its response speed, reversibility, stability, and cyclability for its use in electronic neural networks is discussed.
Thakoor, S.↗
Analog parallel processor hardware for high speed pattern recognition
A VLSI-based analog processor for fully parallel, associative, high-speed pattern matching is reported. The processor consists of two main components: an analog memory matrix for storage of a library of patterns, and a winner-take-all (WTA) circuit for selection of the stored pattern that best matches an input pattern. An inner product is generated between the input vector and each of the stored memories. The resulting values are applied to a WTA network for determination of the closest match. Patterns with up to 22 percent overlap are successfully classified with a WTA settling time of less than 10 microsec. Applications such as star pattern recognition and mineral classification with bounded overlap patterns have been successfully demonstrated. This architecture has a potential for an overall pattern matching speed in excess of 10 exp 9 bits per second for a large memory.
Daud, T.↗
Manganese oxide microswitch for electronic memory based on neural networks
A solid-state, resistance tailorable, programmable-once, binary, nonvolatile memory switch based on manganese oxide thin films is reported. MnO(x) exhibits irreversible memory switching from conducting (on) to insulating (off) state, with the off and on resistance ratio of greater than 10,000. The switching mechanism is current-triggered chemical transformation of a conductive MnO(2-Delta) to an insulating Mn2O3 state. The energy required for switching is of the order of 4-20 nJ/sq micron. The low switching energy, stability of the on and off states, and tailorability of the on state resistance make these microswitches well suited as programmable binary synapses in electronic associative memories based on neural network models.
Ramesham, R.↗