Engineering topics
Publications and source records attributed to Carroll, B. D..
Standard Transistor Array (STAR) design system is semicustom approach to generating random-logic integrated MOS digital circuits. Primary program in STAR system is CAPSTAR, STAR Cell Arrangement Program. CAPSTAR is augmented by automatic routining program, Display program and library of logic cells.
Testing of large scale integrated logic circuits is considered from the point-of-view of automatic test pattern generation. A logic simulator based approach for automatic test pattern generation is taken and is described. The logic model and the timing model used in the simulator are also described. Two methods are presented for generating test patterns from the output of the simulator. Recommendations for future study are also presented.
A brief introduction to the SIMLOG/TESTGN system of programs is given. Detailed instructions on how to use the system are also included. SIMLOG is a logic simulation program. TESTGN is a test pattern generation program.
Instructions are given for updating and maintaining the cell arrangement program for the standard transistor array (CAPSTAR).
The cell placement techniques developed for use with the standard transistor array were incorporated in the cell arrangement program for STAR (CAPSTAR). Instructions for use of this program are given.
A method was developed for the construction of probabilistic state-space models for nonrepairable systems. Models were developed for several systems which achieved reliability improvement by means of error-coding, modularized sparing, massive replication and other fault-tolerant techniques. From the models developed, sets of reliability and coverage equations for the systems were developed. Comparative analyses of the systems were performed using these equation sets. In addition, the effects of varying subunit reliabilities on system reliability and coverage were described. The results of these analyses indicated that a significant gain in system reliability may be achieved by use of combinations of modularized sparing, error coding, and software error control. For sufficiently reliable system subunits, this gain may far exceed the reliability gain achieved by use of massive replication techniques, yet result in a considerable saving in system cost.
Testing of large scale integrated (LSI) logic circuits was considered from the point of view of automatic test pattern generation. A system for automatic test pattern generation is described. A test generation algorithm is presented that can be applied to both combinational and sequential logic circuits. Also included is a programmed implementation of the algorithm and sample results from the program.