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Buehler, Martin G.

Publications and source records attributed to Buehler, Martin G..

39 records · Page 3

Method and apparatus for characterizing propagation delays of integrated circuit devices

Propagation delay of a signal through a channel is measured by cyclically generating a first step-wave signal for transmission through the channel to a two-input logic element and a second step-wave signal with a controlled delay to the second input terminal of the logic element. The logic element determines which signal is present first at its input terminals and stores a binary signal indicative of that determination for control of the delay of the second signal which is advanced or retarded for the next cycle until both the propagation delayed first step-wave signal and the control delayed step-wave signal are coincident. The propagation delay of the channel is then determined by measuring the time between the first and second step-wave signals out of the controlled step-wave signal generator.

Blaes, Brent R.↗

Measuring Conductor Widths and Spacings Electrically

Widths and spacings of conductor lines on integrated circuits measured electrically by split cross-bridge resistor technique. Speeds evaluation of integrated-circuit fabrication processes. When measurement of probe currents and voltages and reduction of measurement data automated, test structure probed and characterized in less than one second.

Buehler, Martin G.↗

An analytical method for predicting CMOS SRAM upsets with application to asymmetrical memory cells

An analytical method was developed to predict the heavy-ion-induced upset rate of static random access memory (SRAM) cells. The method was applied to the design of a memory with asymmetrical cells where the goal was to increase the upset rate in order to increase the number of observed upsets in a space environment. The asymmetry is achieved by increasing the drain area of selected transistors in the cell. Results from the analytical model for a space environment indicate the upset rate for the experimental asymmetrical cell (17.2 upsets/1 kbit-year) will be 4.7 times larger than the upset rate for the minimum-geometry balanced cell (3.6 upsets/1 kbit-year). The asymmetrical SRAM was designed into a test chip intended for the Combined Release and Radiation Effects Satellite (CRRES).

Buehler, Martin G.↗