Time-resolved imaging of microscale dynamics in laser drying of silicon wafers
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Chemistry↗
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Results for “wafer”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Passivated Contacts for Direct Wafer Product (Final Technical Report)
This TCF project developed a thin-oxide (SiO 2 )/polycrystalline silicon (poly-Si) passivated contact solar cell on CubicPV's (formally 1366 Technologies, Inc.) Direct Wafer® Product (DWP) kerfless wafers. The project used two NREL-developed technologies described in U.S. Patent No. 9,911,873, Hydrogenation of Passivated Contacts and U.S. Patent Application Serial No. 15/890,172, Doped Passivated Contacts . The project was motivated by a potential higher efficiency cell (compared to a PERC cell) using passivated contacts on the ultra-low cost kerfless wafers grown using the Direct Wafer process. The hope was to accelerate market adoption of the cell and wafer by delivering the lowest LCOE in the PV industry. The project tested both n-type and p-type SiO 2 /poly-Si passivated contacts grown by thermal oxidation and plasma enhanced chemical vapor deposition (PECVD) of the poly-Si layer on DWP with varying wafer resistivities. Both deposition techniques are industry standards and thus economically viable methods for commercializing the contacts. The results indicated that both n-type and p-type poly-Si passivated contacts can be formed on polycrystalline DWP wafers, but implied open-circuit voltages (i Voc ) were limited to below 0.65 mV (compared with ~ 730 mV on n-Cz wafers). Diffusion of H to the Si/SiO 2 /poly-Si interface was key to obtaining high i Voc values. In this study, H was diffused from a high-temperature SiN x layer deposited over the poly-Si layer during a high-temperature firing step, similar to one used for screen printed metals. The study concluded that poly-Si passivated contacts on DWP wafers passivated the surface of the wafers as well as PERC passivated surfaces, which use a less expensive dielectric layer stack. The project showed that Direct Wafer Product wafers grown by CubicPV could produce high i Voc values (~0.647 mV), which could produce a cell over 20% efficient with proper processing and metallization. These cells, though not economically viable in 2024 as a stand-alone cell, could be integrated with a wide-bandgap top solar cell to form a two-junction tandem cell that could be viable under certain circumstances. This is because the bottom cell of a 30%, two-terminal tandem only needs to be a 20% cell under one-sun conditions. Thus, the DWP could be an ideal low-cost wafer for tandems. The project also revealed that a TOPCon type cell could be formed on a p-type DWP wafer using a P-diffused emitter and a p-type poly-Si contact. In fact, the p-type version of the poly-Si contact out-performed the n-type version for a variety of wafer resistivities, from highly doped to lowly doped. This curiosity requires more work to understand because on Cz wafers, the n-type poly-Si contact is of much higher quality than the p-type version.
14 SOLAR ENERGY↗
System and method for shingling wafer strips connected in parallel
A solar device includes a first string of first solar wafers, wherein a plurality of the first solar wafers each overlap with at least one vertically adjacent solar wafer from the first string. Additionally, the solar device includes a second string of second solar wafers, wherein a plurality of the second solar wafers each overlap with at least one vertically adjacent solar wafer from the second string, wherein a plurality of the first solar wafers overlap with one or more of the plurality of second solar wafers to electrically connect horizontally adjacent solar wafers in parallel.
Caswell, Nathaniel↗
Using machine learning with optical profilometry for GaN wafer screening
Abstract To improve the manufacturing process of GaN wafers, inexpensive wafer screening techniques are required to both provide feedback to the manufacturing process and prevent fabrication on low quality or defective wafers, thus reducing costs resulting from wasted processing effort. Many of the wafer scale characterization techniques—including optical profilometry—produce difficult to interpret results, while models using classical programming techniques require laborious translation of the human-generated data interpretation methodology. Alternatively, machine learning techniques are effective at producing such models if sufficient data is available. For this research project, we fabricated over 6000 vertical PiN GaN diodes across 10 wafers. Using low resolution wafer scale optical profilometry data taken before fabrication, we successfully trained four different machine learning models. All models predict device pass and fail with 70–75% accuracy, and the wafer yield can be predicted within 15% error on the majority of wafers.
36 MATERIALS SCIENCE↗
Wafer-level handle replacement
A wafer includes a number of die, with each die including electronic integrated circuits and optical devices. The wafer has a top surface and a bottom surface and a base layer. The bottom surface of the wafer corresponds to a bottom surface of the base layer. A wafer support system is attached to the top surface of the wafer. A thickness of the base layer is removed to expose a target layer within the wafer and to give the wafer a new bottom surface. A replacement handle structure is attached to the new bottom surface of the wafer. The replacement handle structure includes a first thickness region and a second thickness region. The first thickness region is positioned closest to the new bottom surface. The first thickness region is formed of an optical cladding material that mitigates optical coupling between optical devices within the die and the replacement handle structure.
Meade, Roy Edward↗
Controlled Growth of Single‐Crystal Graphene Wafers on Twin‐Boundary‐Free Cu(111) Substrates
Single-crystal graphene (SCG) wafers are needed to enable mass-electronics and optoelectronics owing to their excellent properties and compatibility with silicon-based technology. Controlled synthesis of high-quality SCG wafers can be done exploiting single-crystal Cu(111) substrates as epitaxial growth substrates recently. However, current Cu(111) films prepared by magnetron sputtering on single-crystal sapphire wafers still suffer from in-plane twin boundaries, which degrade the SCG chemical vapor deposition. Here, in this study, it is shown how to eliminate twin boundaries on Cu and achieve 4 in. Cu(111) wafers with ≈95% crystallinity. The introduction of a temperature gradient on Cu films with designed texture during annealing drives abnormal grain growth across the whole Cu wafer. In-plane twin boundaries are eliminated via migration of out-of-plane grain boundaries. SCG wafers grown on the resulting single-crystal Cu(111) substrates exhibit improved crystallinity with >97% aligned graphene domains. As-synthesized SCG wafers exhibit an average carrier mobility up to 7284 cm 2 V −1 s −1 at room temperature from 103 devices and a uniform sheet resistance with only 5% deviation in 4 in. region.
36 MATERIALS SCIENCE↗
Specific resonance mode enhancement and suppression using non-uniform polarization of piezoelectric wafers: Theory and experiments
In this work, we present experimental demonstration of specific resonance mode enhancement and suppression in circular and rectangular piezoelectric wafers with engineered non-uniform polarization profiles. The polarization profiles are designed based on the electromechanical impedance response of non-uniformly polarized wafers as obtained from the theory. The circular wafers are fabricated with non-uniform polarization profiles that involve a central polarized region surrounded by an unpolarized region. The radius of the polarization zone is designed based on the condition for specific mode enhancement obtained from the electromechanical impedance response of non-uniformly polarized wafers. We actually show how the condition can not only be used to enhance but also to suppress electromechanical resonances. Two kinds of wafers are designed and fabricated to specifically suppress second and third radial modes respectively. Similarly, rectangular wafers are designed with two different kinds of non-uniform polarization profiles — the first of which enhances the second in-plane extensional mode in the impedance spectrum and the second polarization profile suppresses all the electromechanical resonances pertaining to the in-plane extensional modes and selectively excites only the in-plane bending modes. The proposed approach of using non-uniformly polarized wafers finds application in designing multi-frequency sensors/transducers, frequency-tuned receivers, acoustic beamforming, and other non-traditional applications such as information storage.
36 MATERIALS SCIENCE↗
Temperature and illumination dependence of silicon heterojunction solar cells with a wide range of wafer resistivities
Abstract Recently, the significant improvements in the surface and contact passivation of silicon (Si) solar cells as well as their bulk quality have shifted their operating point to higher injections. Hence, they are less dependent on wafer doping. This shift opens an opportunity of using high‐resistivity wafers for practical photovoltaic applications, introducing a promising approach to push the cell efficiency towards the intrinsic limit and to improve the module reliability by increasing the cell breakdown voltage. Therefore, insights into the performance of Si solar cells using high‐resistivity wafers at various operating temperatures are of significant interest. In this study, we investigate the temperature‐ and illumination‐dependent performance of Si heterojunction (SHJ) solar cells using a wide range of wafer resistivities (between 3 and 1000 Ω⋅cm). Although a reduction in the passivation quality of the passivating contacts is observed at elevated temperature, the impact on the temperature coefficient of the open‐circuit voltage (TC V oc )—the dominant contributor to the temperature coefficient (TC) of the cell efficiency—is very limited. Their TC V oc are still dominated by the temperature dependence of the effective intrinsic carrier concentration. Furthermore, we also find that the investigated cells are more sensitive to temperature variation at lower illumination intensities. It is noteworthy that the efficiency of the cells fabricated using high‐resistivity wafers is comparable to that of the reference cells at any given temperature, highlighting the potential of using high‐resistivity wafers for solar cells.
14 SOLAR ENERGY↗
Wafer-Scale Synthesis of 2D Materials by an Amorphous Phase-Mediated Crystallization Approach
The interest in the wafer-scale growth of two-dimensional (2D) materials, including transition metal dichalcogenides (TMDCs), has been rising for transitioning from lab-scale devices to commercial-scale systems. Among various synthesis techniques, physical vapor deposition, such as pulsed laser deposition (PLD), has shown promise for the wafer-scale growth of 2D materials. However, due to the high volatility of chalcogen atoms (e.g., S and Se), films deposited by PLD usually suffer from a lack of stoichiometry and chalcogen deficiency. To mitigate this issue, excess chalcogen is necessary during the deposition, which results in problems like uniformity or not being repeatable. This study demonstrates a condensed-phase or amorphous phase-mediated crystallization (APMC) approach for the wafer-scale synthesis of 2D materials. This method uses a room-temperature PLD process for the deposition and formation of amorphous precursors with controlled thicknesses, followed by a post-deposition crystallization process to convert the amorphous materials to crystalline structures. This approach maintains the stoichiometry of the deposited materials throughout the deposition and crystallization process and enables the large-scale synthesis of crystalline 2D materials (e.g., MoS 2 and WSe 2 ) on Si/SiO 2 substrates, which is critical for future wafer-scale electronics. We show that the thickness of the layers can be digitally controlled by the number of laser pulses during the PLD phase. Optical spectroscopy is used to monitor the crystallization dynamics of amorphous layers as a function of annealing temperature. The crystalline quality, domain sizes, and the number of layers were explored using nanoscale and atomistic characterization (e.g., AFM, STEM, and EDS) along with electrical characterization to explore process–structure–performance relationships. Finally, this growth technique is a promising method that could potentially be adopted in conventional semiconductor industries for wafer-scale manufacturing of next-generation electronic and optoelectronic devices.
2D electronics↗
High-throughput manufacturing of epitaxial membranes from a single wafer by 2D materials-based layer transfer process
Layer transfer techniques have been extensively explored for semiconductor device fabrication as a path to reduce costs and to form heterogeneously integrated devices. These techniques entail isolating epitaxial layers from an expensive donor wafer to form freestanding membranes. However, current layer transfer processes are still low-throughput and too expensive to be commercially suitable. Here we report a high-throughput layer transfer technique that can produce multiple compound semiconductor membranes from a single wafer. We directly grow two-dimensional (2D) materials on III–N and III–V substrates using epitaxy tools, which enables a scheme comprised of multiple alternating layers of 2D materials and epilayers that can be formed by a single growth run. Each epilayer in the multistack structure is then harvested by layer-by-layer mechanical exfoliation, producing multiple freestanding membranes from a single wafer without involving time-consuming processes such as sacrificial layer etching or wafer polishing. Moreover, atomic-precision exfoliation at the 2D interface allows for the recycling of the wafers for subsequent membrane production, with the potential for greatly reducing the manufacturing cost.
77 NANOSCIENCE AND NANOTECHNOLOGY↗
Wafer-Free Crystalline Silicon Solar Cells (CRADA Final Report)
This CRADA project, based on the DOE Solar Energy Technologies Office (SETO) Solar Prize Voucher program, helped Leap Photovoltaics to develop methodologies to immobilize Si particles by permanently attaching them to an Al-coated substrate and thereby forming carrier-selective electrical contacts to the Si particles. The bigger goal was to help Leap Photovoltaics develop these immobilized and contacted particle arrays into relatively efficient, inexpensive, and industrially relevant solar cells. By using Si particles instead of wafers in a solar cell absorber layer, one can avoid costs associated with growing monocrystalline Si ingots, then diamond-sawing them into wafers, then processing wafers into cells – a mainstream practice in today's high-efficiency Si cell and module technology. Monocrystalline or polycrystalline Si particles can be obtained in various ways: for example, Si kerf from wafer sawing is monocrystalline; recycled Si cell wafers can be ball-milled into particles; particles can be grown using various gas-phase techniques (mostly from SiH4). These Si particles can be assembled onto a substrate and serve as an absorber layer for the solar cell, absorbing photons to generate photocarriers. The challenge with this technique is to collect photocarriers from individual Si particles, with separation of photogenerated electrons to the negative cell’s electrode and positive photogenerated holes to the positive electrode. Therefore, each particle must have two isolated, carrier-selective contacts: one for electrons and one for holes. Plus, particles need to be immobilized onto a solid substrate. The goal of this work was focused on the immobilization of Si particles and creating hole-selective contact to them at the same time, using industrially relevant Si photovoltaic (PV) cell technology: screen printing of Al back-surface field electrodes. This is used in the mainstream Propane Education and Research Council (PERC) technology for hole-collecting contacts at the back of the cell. The work performed at NREL consisted of screen printing of Al metal paste on substrates, spreading Si particles onto it, and thermally processing the structures to form hole-collecting contacts. The final structures were investigated by scanning electron microscopy (SEM) after focused ion beam (FIB) cross-sectioning and polishing. The work was done jointly by NREL staff and Leap Photovoltaics (Leap PV) employees stationed at NREL. The samples were then taken to Leap PV for further processing. Training the Leap PV employee on various NREL techniques (laser cutting, screen printing, thermal processing, characterization) was part of the scope.
14 SOLAR ENERGY↗
Acoustics-based noninvasive wafer defect detection
Techniques are provided for detecting wafer defects. Example techniques include exciting a wafer using an acoustic signal to cause the wafer to exhibit vibrations, measuring one or more of linear frequency response metrics or nonlinear frequency responses metrics associated with the vibrations, and identifying any defects in the wafer based at least in part on one or more of the linear frequency response metrics or nonlinear frequency responses metrics. In embodiments, the wafer includes bismuth telluride (Bi 2 Te 3 ).
Pantea, Cristian↗
Integrated Ion-Exchange Membrane Resin Wafer Assemblies for Aromatic Organic Acid Separations Using Electrodeionization
Aromatic acids, such as p-coumaric acid, are valuable chemical intermediates that are used in the specialty chemical industries because they are precursors to phenylpropanoid compounds. The separation of p-coumaric acid from fermentation broths is a critical step in the biochemical production process and more broadly the circular carbon economy. Electrodeionization (EDI) has been applied toward separations of low-carbon chain acids, but purifying p-coumaric acid has been challenging due to fouling and irreversible binding with ion-exchange membranes and resins. Here, we report a new membrane wafer assembly (MWA) consisting of laminated ion exchange membranes to porous ionomer-binder resin wafers for EDI. The MWAs in an EDI stack showed a 7-fold increase in p-coumaric acid capture while also using 70% less specific energy consumption when benchmarked against state-of-the-art resin wafer EDI modules. The more efficient p-coumaric acid recovery was ascribed to (i) the 38% reduction in interfacial transport resistance between the membrane and resin wafer and (ii) using imidazolium anion exchange membranes and ionomer binders in the MWA. MD simulations revealed enhanced transport rates for p-coumarate in imidazolium ionomers through π–π interactions. As a result, adopting the new MWA significantly reduced the amount of ion-exchange membranes in EDI and may lead to drastic capital cost savings.
42 ENGINEERING↗
Generation of selective single-mode guided waves by d 36 type piezoelectric wafer
In general, mixed modes and dispersion of guided wave occur at any excitation frequency, while single modes are needed for effective nondestructive evaluation of structures. In this work, we present an approach to generate a selective single-mode guided wave in plate-like structures by exploiting the unique directionality of the d 36 type piezoelectric wafer and the symmetry of fundamental guided wave modes. Specifically, we devise a unified fundamental shear horizontal (SH 0 ) wave/fundamental antisymmetric mode (A 0 ) wave directional transducer pair by attaching the d 36 type piezoelectric wafers back to back on the opposite sides of the plate to provide selective, directional single-mode guided waves for actuation and sensing. Originally, the d 36 -type piezoelectric wafer, poled and cut from the lead magnesium niobate-lead titanate crystal, produces a mixture of the in-plane SH 0 (symmetric) mode and out-of-plane A 0 (asymmetric) and S 0 (symmetric) modes. By applying the in-phase or out-of-phase applied electrical field to the coupled d 36 -type piezoelectric wafer pair, our devised approach generates selective single modes, SH 0 or A 0 , respectively, to propagate in the structure. We describe the theoretical development of our approach and conduct both numerical simulations and laboratory experiments for validations.
42 ENGINEERING↗
Nature of contaminants introduced in silicon wafers during molecular beam epitaxy chamber annealing
Epitaxial monolithic III–V/Si tandem solar cells are one of the most promising technologies to be adopted by the industry after the efficiency of the current market dominating single junction silicon solar cell saturates at its fundamental limit. One of the key limitations of this technology is the degradation of silicon wafers during in situ annealing in the molecular beam epitaxy chamber. Determining the nature of contaminants in this process is key to improve the efficiency of epitaxial tandem solar cells. However, to date, the nature of contaminants from molecular beam epitaxy chambers remains unknown. In this work, we use photoluminescence imaging, lifetime spectroscopy, and deep level transient spectroscopy to measure the electronic properties of extrinsic impurities incorporated during annealing in the molecular beam epitaxy chamber. Photoluminescence images reveal that at least two impurities diffuse into silicon wafers during molecular beam epitaxy annealing. One is highly localized, while the other one is distributed uniformly across the whole wafer. Phosphorus diffusion is found to confine the localized impurity within the diffused layer but is ineffective at preventing the indiffusion of other impurities. Lifetime spectroscopy shows that metastable impurities with characteristic similar to Cr and CrB in our molecular beam epitaxy annealed silicon wafers. No evidence of Fe or FeB was observed. The emission rates and concentrations of the electrically active defects were measured with deep-level transient spectroscopy: The emission rates of detected defects do not match that of known Cr-related defects.
36 MATERIALS SCIENCE↗
Specifications and pre-production of n + -in-p large-format strip sensors fabricated in 6-inch silicon wafers, ATLAS18, for the Inner Tracker of the ATLAS Detector for High-Luminosity Large Hadron Collider
Abstract The ATLAS experiment is constructing new all-silicon inner tracking system for HL-LHC. The strip detectors cover the radial extent of 40 to 100 cm. A new approach is adopted to use p-type silicon material, making the readout in n + -strips, so-called n + -in-p sensors. This allows for enhanced radiation tolerance against an order of magnitude higher particle fluence compared to the LHC. To cope with varying hit rates and occupancies as a function of radial distance, there are two barrel sensor types, the short strips (SS) for the inner 2 and the long strips (LS) for the outer 2 barrel cylinders, respectively. The barrel sensors exhibit a square, 9.8 × 9.8 cm 2 , geometry, the largest possible sensor area from a 6-inch wafer. The strips are laid out in parallel with a strip pitch of 75.5 μm and 4 or 2 rows of strip segments. The strips are AC-coupled and biased via polysilicon resistors. The endcap sensors employ a “stereo-annulus” geometry exhibiting a skewed-trapezoid shapes with circular edges. They are designed in 6 unique shapes, R0 to R5, corresponding to progressively increasing radial extents and which allows them to fit within the petal geometry and the 6-inch wafer maximally. The strips are in fan-out geometry with an in-built rotation angle, with a mean pitch of approximately 75 μm and 4 or 2 rows of strip segments. The eight sensor types are labeled as ATLAS18xx where xx stands for SS, LS, and R0 to R5. According to the mechanical and electrical specifications, CAD files for wafer processing were laid out, following the successful designs of prototype barrel and endcap sensors, together with a number of optimizations. A pre-production was carried out prior to the full production of the wafers. The quality of the sensors is reviewed and judged excellent through the test results carried out by vendor. These sensors are used for establishing acceptance procedures and to evaluate their performance in the ATLAS collaboration, and subsequently for pre-production of strip modules and stave and petal structures.
Instruments & Instrumentation↗
Wafer-scale waveguide sidewall roughness scattering loss characterization by image processing
Photonic integrated circuits (PICs) are vital for developing affordable, high-performance optoelectronic devices that can be manufactured at an industrial scale, driving innovation and efficiency in various applications. Optical loss of modes in thin film waveguides and devices is a critical measure of their performance. Thin film growth, lithography, masking, and etching processes are imperfect processes that introduce significant sidewall and top-surface roughness and cause dominating optical losses in waveguides and photonic structures. This roughness, as perturbations couple light from guided to far-field radiation modes, leads to scattering losses that can be estimated from theoretical models. Typically, with UV-based lithography, sidewall roughness is significantly larger than wafer-top surface roughness. Atomic force microscopy (AFM) imaging measurement gives a 3D and high-resolution roughness profile, but the measurement is inconvenient, costly, and unscalable for large-scale PICs and at wafer-scale. Here, we evaluate the sidewall roughness profile based on 2D high-resolution scanning electron microscope (SEM) imaging. We characterized the loss on two homemade nitride and oxide films on 3-inch silicon wafers with 12 waveguide devices on each and correlated the scattering loss estimated from a 2D image-based sidewall profile and theoretical Payne model. The lowest loss of guided fundamental transverse electric (TE 0 ) mode is found at 0.075 dB/cm at 633 nm across 24 devices, a record at visible wavelength. Our work shows 100% success (edge continuity span exceeding 95% of image width/height) in edge detection in image processing of all images to estimate autocorrelation function and optical mode loss. These demonstrations offer valuable insights into waveguide sidewall roughness and a comparison of experimental and 2D SEM image processing based loss estimations with applications in loss characterization at wafer-scale PICs.
Khurana, Mohit (ORCID:0000000207898672)↗