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All sources NASA NTRS DOE OSTI

NASA NTRS2010

Advanced Flip Chips in Extreme Temperature Environments

The use of underfill materials is necessary with flip-chip interconnect technology to redistribute stresses due to mismatching coefficients of thermal expansion (CTEs) between dissimilar materials in the overall assembly. Underfills are formulated using organic polymers and possibly inorganic filler materials. There are a few ways to apply the underfills with flip-chip technology. Traditional capillary-flow underfill materials now possess high flow speed and reduced time to cure, but they still require additional processing steps beyond the typical surface-mount technology (SMT) assembly process. Studies were conducted using underfills in a temperature range of -190 to 85 C, which resulted in an increase of reliability by one to two orders of magnitude. Thermal shock of the flip-chip test articles was designed to induce failures at the interconnect sites (-40 to 100 C). The study on the reliability of flip chips using underfills in the extreme temperature region is of significant value for space applications. This technology is considered as an enabling technology for future space missions. Flip-chip interconnect technology is an advanced electrical interconnection approach where the silicon die or chip is electrically connected, face down, to the substrate by reflowing solder bumps on area-array metallized terminals on the die to matching footprints of solder-wettable pads on the chosen substrate. This advanced flip-chip interconnect technology will significantly improve the performance of high-speed systems, productivity enhancement over manual wire bonding, self-alignment during die joining, low lead inductances, and reduced need for attachment of precious metals. The use of commercially developed no-flow fluxing underfills provides a means of reducing the processing steps employed in the traditional capillary flow methods to enhance SMT compatibility. Reliability of flip chips may be significantly increased by matching/tailoring the CTEs of the substrate material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.

Ramesham, Rajeshuni↗

NASA NTRS2003

Pressure-Sensor Assembly Technique

Nielsen Engineering & Research (NEAR) recently developed an ultrathin data acquisition system for use in turbomachinery testing at NASA Glenn Research Center. This system integrates a microelectromechanical- systems- (MEMS-) based absolute pressure sensor [0 to 50 psia (0 to 345 kPa)], temperature sensor, signal-conditioning application-specific integrated circuit (ASIC), microprocessor, and digital memory into a package which is roughly 2.8 in. (7.1 cm) long by 0.75 in. (1.9 cm) wide. Each of these components is flip-chip attached to a thin, flexible circuit board and subsequently ground and polished to achieve a total system thickness of 0.006 in. (0.15 mm). Because this instrument is so thin, it can be quickly adhered to any surface of interest where data can be collected without disrupting the flow being investigated. One issue in the development of the ultrathin data acquisition system was how to attach the MEMS pressure sensor to the circuit board in a manner which allowed the sensor s diaphragm to communicate with the ambient fluid while providing enough support for the chip to survive the grinding and polishing operations. The technique, developed by NEAR and Jabil Technology Services Group (San Jose, CA), is described below. In the approach developed, the sensor is attached to the specially designed circuit board, see Figure 1, using a modified flip-chip technique. The circular diaphragm on the left side of the sensor is used to actively measure the ambient pressure, while the diaphragm on the right is used to compensate for changes in output due to temperature variations. The circuit board is fabricated with an access hole through it so that when the completed system is installed onto a wind tunnel model (chip side down), the active diaphragm is exposed to the environment. After the sensor is flip-chip attached to the circuit board, the die is underfilled to support the chip during the subsequent grinding and polishing operations. To prevent this underfill material from getting onto the sensor s diaphragms, the circuit board is fabricated with two 25- micrometer-tall polymer rings, sized so that the diaphragms fit inside the rings once the chip is attached.

Pruzan, Daniel A.↗

NASA NTRS2017

Applications of Fracture Mechanics to Quantitative Accelerated Life Testing of Plastic Encapsulated Microelectronics

Accelerated testing must address the failure mechanisms active within the devices undergoing tests in order to assess lifetimes in a meaningful way. The assumption of constant temperature, thermally activated lifetime, based upon the Arrhenius assumptions, does not always provide the necessary understanding to interpret accelerated tests in microelectronics. Plastic encapsulants, dielectric polymers, and underfill materials are subject to delamination and cracking with thermal cycling. Crack propagation during use environment exposure, drives the potential for failure of microelectronic devices and is therefore a necessary focal point in qualification and life testing. This paper reviews the available research in the application of fracture mechanics to this class of problems in microelectronics including relevant test data. In addition, useful acceleration factor models are derived for polymer crack propagation based on principles of linear elastic fracture mechanics. Further, a simple approach to estimating the minimum temperature cycling ranges, necessary to propagate a crack, is also presented. Finally, a methodology of applying acceleration factors to develop testing plans is shown, with an example in spaceflight for a cubesat in low Earth orbit. Overall, this is a paper that shows a useful and appropriate process for creating physics of failure based life testing for delamination and cracking failures in microelectronic polymers in a temperature cycling environment.

Accelerated testing↗

DOE OSTI2024

Radiopaque particle processing additive

A radiopaque processing medium comprising a plurality of radiopaque particles and a non-radiopaque processing medium. The plurality of radiopaque particles is added to the non-radiopaque processing medium to increase a bulk density of the processing medium thereby forming the radiopaque processing medium. The radiopaque processing medium allows excess process media to be located and characterized during X-ray inspection of an electronic device on which the radiopaque processing medium was used. The radiopaque processing medium may also be used to locate and identify flaws/defects of the electronic device based on the location of excess radiopaque processing medium. The radiopaque processing medium may also be used as an underfill material to reinforce electronic chips soldered to the electronic device.

Diamond, Louis↗

NASA NTRS2013

Physics of Failure Analysis of Xilinx Flip Chip CCGA Packages: Effects of Mission Environments on Properties of LP2 Underfill and ATI Lid Adhesive Materials

The Xilinx Virtex 4QV and 5QV (V4 and V5) are next-generation field-programmable gate arrays (FPGAs) for space applications. However, there have been concerns within the space community regarding the non-hermeticity of V4/V5 packages; polymeric materials such as the underfill and lid adhesive will be directly exposed to the space environment. In this study, reliability concerns associated with the non-hermeticity of V4/V5 packages were investigated by studying properties and behavior of the underfill and the lid adhesvie materials used in V4/V5 packages.

Suh, Jong-ook↗

NASA NTRS2013

Physics of failure analysis of Xilinx Flip Chip CCGA packages: effects of mission environments on properties of LP2 underfill and ATI lid adhesive materials

Suh, Jong-ook↗

DOE OSTI2025

Material Needs and Measurement Challenges for Advanced Semiconductor Packaging: Understanding the Soft Side of Science

This Perspective builds upon insights from the National Institute of Standards and Technology (NIST)-organized workshop, “Materials and Metrology Needs for Advanced Semiconductor Packaging Strategies,” held at the 35th annual Electronics Packaging Symposium in Binghamton, NY, on September 5, 2024. It outlines critical challenges and opportunities related to polymer-based “soft” materials in advanced semiconductor packaging, with emphasis on polymer science, measurement science (metrology), and the strategic development of Research-Grade Test Materials (RGTMs). These efforts, led by the NIST CHIPS team, aim to advance the fundamental understanding of structure-property-processing relationships, promote standardized guidelines and innovative methods for material characterization, and accelerate the development, qualification, and adoption of next-generation packaging materials. The Perspective also distills key insights from the panel discussion with industry experts, emphasizing the need for close collaboration among materials scientists, process engineers, and metrology experts to enable a holistic strategy, further highlighting the importance of cross-sector partnerships among industry, academia, and government to address pressing challenges in packaging materials and processes.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS2014

Aeroflex Technology as Class-Y Demonstrator

Modern space field programmable gate array (FPGA) devices with increased functional density and operational frequency, such as Xilinx Virtex 4 (V4) and S (V5), are packaged in non-hermetic ceramic flip chip forms. These next generation space parts were not qualified to the MIL-PRF-38535 Qualified Manufacturer Listing (QML) class-V when they were released because class-V was only intended for hermetic parts. In order to bring Xilinx V5 type packages into the QML system, it was suggested that class-Y be set up as a new category. From 2010 through 2014, a JEDEC G12 task group developed screening and qualification requirements for Class-Y products. The Document Standardization Division of the Defense Logistics Agency (DLA) has completed an engineering practice study. In parallel with the class-Y efforts, the NASA Electronic Parts and Packaging (NEPP) program has funded JPL to study potential reliability issues of the class-Y products. The major hurdle of this task was the absence of adequate research samples. Figure 1-1 shows schematic diagrams of typical structures of class-Y type products. Typically, class-Y products are either in ceramic flip chip column grid array (CGA) or land grid array (LGA) form. In class-Y packages, underfill and heat spread adhesive materials are directly exposed to the spacecraft environment due to their non-hermeticity. One of the concerns originally raised was that the underfill material could degrade due to the spacecraft environment and negatively impact the reliability of the package. In order to study such issues, it was necessary to use ceramic daisy chain flip chip package samples so that continuity of flip chip solder bumps could be monitored during the reliability tests. However, none of the commercially available class-Y daisy chain parts had electrical connections through flip chip solder bumps; only solder columns were daisy chained, which made it impossible to test continuity of flip chip solder bumps without using extremely costly functional parts. Among space parts manufacturers who were interested in producing class-Y products, Aeroflex Microelectronic Solutions-HiRel had been developing assembly processes using their internal R&D classy type samples. In early 2012, JPL and Aeroflex initiated a collaboration to study reliability of the Aeroflex technology as a class-Y demonstrator.

Suh, Jong-ook↗

DOE OSTI2025

Predictive dynamic wetting, fluid–structure interaction simulations for braze run-out

Brazing and soldering are metallurgical joining techniques that use a wetting molten metal to create a joint between two faying surfaces. Here, the quality of the brazing process depends strongly on the wetting properties of the molten filler metal, namely the surface tension and contact angle, and the resulting joint can be susceptible to various defects, such as run-out and underfill, if the material properties or joining conditions are not suitable. In this work, we implement a finite element simulation to predict the formation of such defects in braze processes. This model incorporates both fluid–structure interaction through an arbitrary Eulerian–Lagrangian technique and free surface wetting through conformal decomposition finite element modeling. Upon validating our numerical simulations against experimental run-out studies on a silver-Kovar system, we then use the model to predict run-out and underfill in systems with variable surface tension, contact angles, and applied pressure. Finally, we consider variable joint/surface geometries and show how different geometrical configurations can help to mitigate run-out. This work aims to understand how brazing defects arise and validate a coupled wetting and fluid–structure interaction simulation that can be used for other industrial problems.

36 MATERIALS SCIENCE↗

DOE OSTI2025

Defect Detection Model Development for Large Scale Thermoplastic Printing

Large-format additive manufacturing (LFAM) offers several advantages, including high throughput, cost-effective pellet-fed extrusion, and the capability to produce large-scale structures. The main pain points of LFAM include start and stops during the printing process, warpage, long layer times that lead to bead freezing, and bead separation due to shrinkage. These issues can lead to overfill, underfill and buildup of material in different sections of a print. This can lead to hidden defects embedded within the printed layers, or even ultimate failure of the printed structure. This ensures these defects can only be identified through nondestructive testing (NDT) inspection methods after printing, which can be timely and costly. Aligned Vision work specializes in 2D projectors with visual inspection systems and machine learning. Traditionally system is used for composite layup and layup inspections. In this work we used the LFAM system at Oak Ridge National Laboratory to create defect rich samples. The Aligned Vision inspection system then performed in-situ monitoring of the print process after each part was printed. This in-situ vision inspection system was used to develop a layer-by-layer inspection model that looks for overfill, underfill, and the buildup of defects using only a camera-based vision system. This leads to the assurance of high-quality production components.

36 MATERIALS SCIENCE↗

NASA NTRS2010

System on a Chip (SoC) Overview

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions all on a single chip substrate. Complexity drives it all: Radiation tolerance and testability are challenges for fault isolation, propagation, and validation. Bigger single silicon die than flown before and technology is scaling below 90nm (new qual methods). Packages have changed and are bigger and more difficult to inspect, test, and understand. Add in embedded passives. Material interfaces are more complex (underfills, processing). New rules for board layouts. Mechanical and thermal designs, etc.

LaBel, Kenneth A.↗

NASA NTRS2014

AE (Acoustic Emission) for Flip-Chip CGA/FCBGA Defect Detection

C-mode scanning acoustic microscopy (C-SAM) is a nondestructive inspection technique that uses ultrasound to show the internal feature of a specimen. A very high or ultra-high-frequency ultrasound passes through a specimen to produce a visible acoustic microimage (AMI) of its inner features. As ultrasound travels into a specimen, the wave is absorbed, scattered or reflected. The response is highly sensitive to the elastic properties of the materials and is especially sensitive to air gaps. This specific characteristic makes AMI the preferred method for finding "air gaps" such as delamination, cracks, voids, and porosity. C-SAM analysis, which is a type of AMI, was widely used in the past for evaluation of plastic microelectronic circuits, especially for detecting delamination of direct die bonding. With the introduction of the flip-chip die attachment in a package; its use has been expanded to nondestructive characterization of the flip-chip solder bumps and underfill. Figure 1.1 compares visual and C-SAM inspection approaches for defect detection, especially for solder joint interconnections and hidden defects. C-SAM is specifically useful for package features like internal cracks and delamination. C-SAM not only allows for the visualization of the interior features, it has the ability to produce images on layer-by-layer basis. Visual inspection; however, is only superior to C-SAM for the exposed features including solder dewetting, microcracks, and contamination. Ideally, a combination of various inspection techniques - visual, optical and SEM microscopy, C-SAM, and X-ray - need to be performed in order to assure quality at part, package, and system levels. This reports presents evaluations performed on various advanced packages/assemblies, especially the flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. Both external and internal equipment was used for evaluation. The outside facility provided images of the key features that could be detected using the most advanced C-SAM equipment with a skilled operator. Investigation continued using in-house equipment with its limitations. For comparison, representative X-rays of the assemblies were also gathered to show key defect detection features of these non-destructive techniques. Key images gathered and compared are: Compared the images of 2D X-ray and C-SAM for a plastic LGA assembly showing features that could be detected by either NDE technique. For this specific case, X-ray was a clear winner. Evaluated flip-chip CGA and FCBGA assemblies with and without heat sink by C-SAM. Only the FCCGA package that had no heat sink could be fully analyzed for underfill and bump quality. Cross-sectional microscopy did not revealed peripheral delamination features detected by C-SAM. Analyzed a number of fine pitch PBGA assemblies by C-SAM. Even though the internal features of the package assemblies could be detected, C-SAM was unable to detect solder joint failure at either the package or board level. Twenty times touch ups by solder iron with 700degF tip temperature, each with about 5 second duration, did not induce defects to be detected by C-SAM images. Other techniques need to be considered to induce known defects for characterization. Given NASA's emphasis on the use of microelectronic packages and assemblies and quality assurance on workmanship defect detection, understanding key features of various inspection systems that detect defects in the early stages of package and assembly is critical to developing approaches that will minimize future failures. Additional specific, tailored non-destructive inspection approaches could enable low-risk insertion of these advanced electronic packages having hidden and fine features.

Ghaffarian, Reza↗

DOE OSTI2024

Solidification of SRPPF Aqueous Recovery Liquid: Process Disruptions

Savannah River National Laboratory has identified a magnesium oxysulfate grout formulation to solidify the liquid effluent from the Savannah River Plutonium Processing Facility (SRPPF) Aqueous Recovery System (ARS). The formulation uses reactive, light burnt MgO, anhydrous MgSO 4 , and dead burnt MgO and provides good mixability, similar density to the original Portland Cement-based mix, and a leachate pH of 9.39, within the assumed Waste Isolation Pilot Plant (WIPP) brine pH range. The formulation will solidify the effluent using a solid first, lost paddle design, within a 55-gallon drum. A series of seven different process disruptions, or irregular processing during the expected ARS liquid effluent solidification process, were completed to assess the severity of the impact of the process disruption and how the formulation behaves under these conditions. Seven process disruptions were investigated including: No Mixing, Partial Mixing, Compacted/Stratified, Sealed, Overfilled, Underfilled, and Undermixed. The impact on solidification, leachate pH, Er (a Pu/Am surrogate) distribution, and density of the resulting grout were established. Overall, four of the process disruptions, No Mixing, Partial Mixing, Compacted/Stratified, and Overfilled, resulted in basic, unabsorbed liquid that would require additional solidification to be acceptable for WIPP. Most solids generated in this testing met the expected WIPP leachate pH requirements. Solids from the Compacted/Stratified process disruption test, however, produced a leachate pH slightly above the assumed range in the WIPP performance assessment. The distribution of Er for most of the tests was relatively consistent. The No Mixing process disruption test, however, resulted in non-homogeneous Er distribution, indicating that radioactive material would not be evenly distributed throughout this solid’s matrix. The Overfilled test is the only mix with a density slightly below the acceptable value. The Sealed and Overmixed tests produced a solid closest to the standard mix with no unabsorbed liquid, expected leachate pH levels, consistent Er concentrations, and expected density, indicating these process disruptions do not have a negative impact on the final grout form. Based on the other process disruptions, it is critical to have premixed dry materials and a well-defined mixing process to produce a solid, homogeneous magnesium oxysulfate cement, with no unabsorbed liquid. These process disruption tests show that the lack of adequate mixing is fundamental to creating an improperly solidified material that may require remediation.

12 MANAGEMENT OF RADIOACTIVE AND NON-RADIOACTIVE W↗

DOE OSTI2025

Pressure suppresses the density wave order in kagome metal LuNb 6 ⁢Sn 6

The density waves that develop in kagome metals ScV 6 ⁢Sn 6 and LuNb 6 ⁢Sn 6 at low temperature appear to arise from underfilled atomic columns within a V-Sn or Nb-Sn scaffolding. Compressing this network with applied pressure in ScV 6 ⁢Sn 6 suppressed the structural transition temperature by constraining atomic rattling and inhibiting the shifts that define the structural modulation. We predicted that the density wave transition in LuNb 6⁢ Sn 6 at 68 K would be suppressed by pressure as well. In this Letter, we examine the pressure dependence of the density wave transition by measuring resistance vs temperature up to 2.26 GPa. We found the transition temperature is smoothly depressed and disappears around 1.9 GPa. In conclusion, this result not only addresses our prediction, but strengthens the rattling chains origin of structural instabilities in the HfFe 6⁢ Ge 6 -type kagome metals.

Charge density waves↗