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At least 19 records

A Vertical GaN-Based Neutral-Pointless Three-Level Inverter for High-Performance Automotive Traction Applications

Silicon Carbide (SiC) MOSFETs have emerged as a dominant solution for electric vehicle traction inverters because of their superior power density and efficiency compared to Silicon (Si) counterparts. However, SiC devices possess inherent switching speed limitations that constrain the maximum switching frequency and hinder further power density and efficiency improvements. To address these limitations, this paper proposes a vertical Gallium Nitride (vGaN) based X-type Neutral-Pointless (NPL.X) three-level (3L) inverter for an 800V, 200 kW traction system. Integrating 700V vGaN technology within the NPL.X 3L topology enables improved drive efficiency and higher switching frequencies, resulting in enhanced power density and output power quality. To evaluate the performance benefits, this work conducts a comprehensive loss characterization of the vGaN￾based NPL.X topology, providing a direct comparison with a SiC￾based two level (2L) inverter. The results show that the proposed vGaN-based inverter achieves superior efficiency, particularly within the low-torque regions that dominate standard automotive drive cycles. The proposed vGaN-based inverter represents a critical advancement toward high-power-density and high efficiency traction drives

Halawa, Ali [Purdue Univ., West Lafayette, IN (Uni↗

A Six-Phase Space Vector PWM Technique for Wide Bandgap Device-Based Three-Level Inverters

This article presents a space vector pulsewidth modulation (SVPWM) technique for wide bandgap (WBG) device-based three-level (3L) six-phase inverters. Implementation of the SVPWM techniques for any six-phase inverter is complex for its high number of possible voltage vectors. Different six-phase load configurations are also possible depending on the angle between two consecutive phases and neutral point connections. The implementation techniques change depending on the load configuration. Moreover, a common neutral point for all six phases leads to circulating currents. Capacitor voltage balancing is also needed for 3L inverters. Capacitor voltage balancing and addressing the circulating current problem further increases the implementation complexity. In this article, a generalized SVPWM technique is proposed for the six-phase 3L inverters that is implementable using two three-phase 3L SVPWM blocks. The SVPWM technique also ensures dc bus capacitor voltage balancing and minimizes circulating current. Here, the SVPWM technique is experimentally verified using a GaN-based 3L six-phase active neutral point clamped (ANPC) inverter prototype, and the results are presented in this article.

42 ENGINEERING↗

Postfault Operation of Three-Level Inverter Driven Six-Phase PMSM With Enhanced Torque–Speed Region

This article presents an open-switch postfault operational technique with enhanced torque–speed region for three-level (3L) active neutral point clamped (ANPC) inverter-driven symmetrical six-phase (SSP) permanent magnet synchronous machines (PMSMs). Maximum torque (MT), minimum loss (ML), and single three-phase (STP) operations are commonly used for the postfault operations of six-phase drives. The maximum possible torque and speed in these operations are generally limited by voltage, current ratings, and the neutral point configuration of the motor. To enhance the postfault torque and speed operating region, the torque and speed limits in different postfault operational techniques are determined based on the voltage, current constraints, and neutral point configuration of the SSP-PMSM. In this work, a unified postfault operation is proposed that increases the postfault operational limits by combining MT, ML, and STP operations and modifying the neutral point configuration of the SSP-PMSM. In addition, a technique is also presented that modifies the pulsewidth modulation technique to enable full torque operation below 0.5 p.u. speed. The proposed postfault operational technique enables full-speed (1 p.u.) operation by operating in STP mode and full torque operation (1 p.u.) below 0.5 p.u. speed. Furthermore, the postfault operational technique is experimentally validated using a Gallium Nitride (GaN) device-based3L-ANPC inverter-driven SSP-PMSM.

42 ENGINEERING↗

Three-phase, three-level inverters and methods for performing soft switching with phase synchronization

A three-phase, N-level inverter and method are disclosed. A circuit topology of the inverter comprises first, second and third sets of switches and first, second and third inductors. Each switch comprises at least first, second and third terminals, the first terminals being control terminals. The first terminals of the first, second and third inductors are electrically coupled to the first, second and third sets of switches, respectively. A current controller performs a control algorithm that causes it to output first, second and third sets of gating signals to the control terminals of the switches of the first, second and third sets of switches, respectively, to cause them to be placed in an on state or an off state in a particular sequence to perform zero voltage switching while maintaining synchronization of the three phases of the three-phase, N-level inverter.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Power Layout Design of a GaN HEMTs-Based High-Power High-Efficiency Three-Level ANPC Inverter for 800 V DC Bus System

Multiple commutation paths exist for switching devices in a three-level active neutral point clamped (3L-ANPC) inverter operation based on the selected switching state and current direction. In addition, the capacitive coupling path of the nonswitching device is a key design aspect for enabling high voltage and high current operation of gallium nitride (GaN) switches in 3L-ANPC topology. A comprehensive study of the switching transient events of inner, outer, and clamping devices of 3L-ANPC is presented in this article. The commutation mechanisms for worst-case transient voltage overshoots (TVOs) are identified. A simplified equivalent circuit model is presented to determine the design criteria for the power layout structure's parasitic inductances. A power layout strategy satisfying the design criteria is then proposed using an insulated metal substrate power printed circuit board (PCB) to enable efficient high-power operation. The proposed design minimizes the commutation and capacitive coupling path inductances to 6 nH and 11.5 nH, respectively. This enables the fast switching operation of GaN HEMTs at 800 V dc, 36 A with a low TVO of 31% verified through experimental three-level double pulse test results. Experimental evaluation of a three-phase 3L-ANPC hardware prototype based on the proposed power layout shows 99% efficiency at 800 V, 9.5 kVA and 50 kHz switching frequency. The proposed design achieves a low case-to-ambient thermal resistance of 2.3 °C/W.

42 ENGINEERING↗

Reliability Improvement by Fault-Tolerant Operation of NPC Inverter for Motor Driving

The high-reliability operation of three-level inverters is crucial to prevent equipment damage, process downtime, and economic losses. This article investigates a three-level neutral-point-clamped inverter under all possible combinations of open-circuit and short-circuit faults and proposes a new postfault operation method without adding extra hardware. This method provides comprehensive solution for operations after single and multiple-device failures, increasing the inverter reliability by 24%. This article classified postfault modulations and uncovered previously unknown fault scenarios that can be addressed using the proposed control method. A new postfault modulation based on space vector modulation with virtual vectors is proposed. The feasibility of the proposed control method is verified by simulation and an experiment for one fault scenario in a three-level neutral-point-clamped inverter with a 3.73 kW motor load. Furthermore, this article contributes to improving the reliability of three-level inverters.

42 ENGINEERING↗

Next-Generation, High-temperature, High-frequency, High-efficiency, High-power-density Traction System

To meet performance and reliability requirements necessary for broader adoption of electric drive vehicles, the Electrical and Electronics Technical Team of the U.S. Drive partnership has established aggressive design goals for next-generation electric vehicle drivetrains. Specifically, the 2025 roadmap stipulates a 100 kW/L power density target and a $\$$2.7/kW cost target for power electronics, in addition to high-voltage operation (i.e., greater than 800 VDC). The additional targets for traction motor and the overall system performance impose further challenges on the power electronics design. For example, many high specific power machines have reduced iron content, and therefore reduced intrinsic filtering, thus requiring the inverter to supply a low-distortion drive current. These machines also typically have a high pole count, thus requiring drive current at a higher electrical frequency. Other motors, such as brush-less dc and switch reluctance machines, require a carefully-shaped, non-sinusoidal drive current (Yang, Shang, Brown, & Krishnamurthy, 2015), (Zhang, Bowman, O'Connel, & Haran, 2018), (Anderson, et al., 2018). Two- and three-level inverter topologies are the conventional framework for the power electronics design of the drivetrain, and some demonstrations have shown recent progress towards addressing cost, power density and efficiency goals (Gurpinar & Ozpineci, 2018), (Zhu, Kim, Chen, Erickson, & Maksimović, 2018), (Deshpande, Chen, Narayanasamy, Sathyanarayanan, & Luo, 2018), (Alizadeh, et al., 2019). However, an unconventional approach may be necessary to take the dramatic leap in power density necessitated by the roadmap—while simultaneously addressing the other system needs. Therefore, this project leverages the flying capacitor multilevel (FCML) topology, together with a scalable, modular approach, to address these needs. This type of hybrid converter has several advantages: lower voltage (i.e., less than 300 V) transistors can be used, energy-dense capacitors process most of the power, and the output current waveform is multilevel and exhibits a frequency multiplying effect—in other words, the output has reduced dv/dt and filtering requirements for the same high voltage dc bus. For example, in an electric vehicle with an 800 V bus, a 10-level FCML could leverage 100 V, commercially available GaN devices switching at 115 kHz to produce a ~1 MHz switching waveform (modulated according to the motor drive requirements) with one ninth of the dv/dt of a two-level converter. Prior work has already demonstrated promising performance and gravimetric power density figures for more electric aircraft applications (Pallo, Foulkes, Modeer, Coday, & Pilawa-Podgurski, 2018). This project leverages lessons learned to achieve the volumetric power density of 100 kW/L by employing advanced liquid cooling, address the 300,000 mile reliability challenge with redundant design, topology failure studies and online health monitoring, and reduce costs to $\$$2.7/kW through the use of low-cost GaN devices, modular converter assemblies, and modest modifications to traditional manufacturing methods. The project involved several hardware designs, each achieving increasing performance. At the conclusion of the project, a volumetric power density of 380 kW/L was achieved, in a 800V dc-ac converter, greatly surpassing even the aggressive target goal.

33 ADVANCED PROPULSION SYSTEMS↗

DC-Link Capacitor Design for a Neutral-Point-Less Three-Level Dual-Phase Inverter for Traction Application

Conventional multilevel inverters, such as neutral￾point-clamped and T-type inverters, have gained popularity in electric vehicle applications due to their advantages, including high voltage range, high power capability, low switching losses, low total harmonic distortion, and low electromagnetic interference. However, these traditional multilevel inverters require a neutral point connection to generate a zero-voltage vector. The neutral point current oscillates at three times the fundamental frequency, leading to voltage imbalance and overvoltage stress on the power modules. Additionally, the use of two stacked DC-link capacitors increases the volume required for the same overall capacitance and complicates packaging due to ripple current and heat dissipation from separate components. This is a significant concern for traction drive units, where space is limited. In this paper, a neutral-point-less multilevel dual three￾phase inverter topology is investigated for traction inverter applications. Simulation results demonstrate that the proposed topology effectively retains the benefits of multilevel operation while utilizing a single DC-link capacitor. The inverter model was simulated in conjunction with an industry-standard battery model to evaluate the potential for capacitor size reduction compared to a conventional three-level inverter.

33 ADVANCED PROPULSION SYSTEMS↗

Switching Modes for Reduction of Peak Voltage Transients in GaN-Based Three Level ANPC Inverter

The switching pole voltage can transition between P,0, and N states in a three-level active neutral point clamped (ANPC) inverter. State transitions between 0-P and 0-N can be realized with different switching modes. Three switching modes- Short 1 , Short 2 , and Full are studied considering the effect of capacitive current paths. The role of clamping and inner switch on/off conditions is determined using simplified equivalent circuit models. Short 2 with clamping switch off is beneficial for turn-on overvoltage suppression but results in high turn-off overvoltage. Full mode with a parallel current sharing path is effective for turn-off overvoltage suppression but leads to high turn-on overvoltage. Hence, a Modified Full mode is proposed to achieve the simultaneous objective of overvoltage suppression at both turn-on and turn-off transient during high load currents. This benefits 3L ANPC operation at a low power factor with a high load current at fundamental voltage zero crossing points. Here, a 650V GaN-based three-level ANPC inverter prototype is designed and used to evaluate the switching modes and overvoltage suppression strategies through double pulse tests and continuous operation.

42 ENGINEERING↗

Busbar Design and Optimization for Voltage Overshoot Mitigation of a Silicon Carbide High-Power Three-Phase T-Type Inverter

The silicon carbide (SiC) devices have faster switching speed than that of the conventional silicon (Si) devices, which however may cause excessive device voltage overshoot. Larger gate resistance can help to restrain the overshoot, it however slows down the switching speed and increases switching losses. There are other methods that can mitigate the voltage overshoot, e.g., using low-inductance busbars, adding snubber circuits, etc. In this article, the busbar design for a 250-kW SiC three-level T-type inverter is investigated. The current commutation loops (CCLs) are first analyzed using a single-phase equivalent circuit. Then the detailed busbar design methods, especially a 3-D busbar design concept, are proposed to select the optimal stacking order for the multilayer laminated busbar and to address constraints posed by the physical terminal arrangements of SiC modules and dc-link capacitors. The stray inductance in each CCL is extracted via a finite element analysis and validated on the actual inverter busbar prototypes using an impedance analyzer. To further minimize the busbar stray inductance, a hybrid busbar structure with printed circuit board based buffer circuit using high-frequency decoupling capacitors is designed and evaluated in this article. Lastly, the effectiveness of the designed busbars as well as the buffer circuit are validated using experimental studies.

42 ENGINEERING↗

A Digital Three Level Space Vector Modulator for High Frequency Vector Sequence Generation

This letter proposes a digital high-speed three-level space vector pulse width modulator (3L-SVPWM). A conventional 3L-SVPWM is typically computation-based, involving a sequential execution of sub-tasks on a digital signal processor (DSP) based controller. The resulting high computation time of 5.4 μs limits the implementation of additional control blocks for switching frequencies greater than 100 kHz. This is overcome by transforming sub-tasks into digital blocks with 1-0 decisions and simpler arithmetic operations. The sub-task blocks are executed concurrently on a programmable logic device (PLD). Hence, a fast 3L-SVPWM execution in 140 ns is achieved. The proposed digital 3L-SVPWM enables high switching frequency operation of wide bandgap (WBG) device-based 3 L inverters to generate high fundamental frequency waveforms. A finite state machine is an integral part of the proposed implementation with the ability to generate any vector sequence, maximizing the usage of redundant vector states in 3L-SVPWM. Here, the proposed digital 3L-SVPWM operation is demonstrated with a GaN-based 3 L active neutral point clamped (3L-ANPC) inverter. Experimental results are presented at 250 kHz switching frequency to generate vector sequences for center-aligned SVPWM (CA-SVPWM) and common mode voltage reduced SVPWM (CMVR-SVPWM). The results also showcase a high fundamental frequency generation capability of 10 kHz.

active neutral point clamped inverter↗

Experiences and Lessons from Field Demonstration of Grid-forming Inverter in An AC Microgrid

The validation of GFM control strategies through simulation and hardware demonstration is important before their large-scale deployments in the real grid. Considering the importance of testing and validation, several works have explored the GFM inverter’s capability to blackstart a microgrid, synchronize and share loads, and interact with various types of generation sources and loads present in the grid. Herein, this paper complements the existing works by presenting the results and analysis of a field demonstration in an actual AC microgrid. The capability of a three-level neutral point clamped (NPC) GFM inverter equipped with a recursive feedback type of non-linear device level control to operate with PV source on its DC input and off-the-shelf PVGFL inverters and EV chargers of different kinds on the AC side is explored. The analysis and conclusions drawn would inform the readers to make better decisions during the field demonstration process.

24 POWER TRANSMISSION AND DISTRIBUTION↗

A Voltage Injection-Based Current Harmonics Suppression Strategy for Six-Phase PMSM With Nonsinusoidal Back EMF

This article presents a voltage injection-based current harmonic minimization method for wide bandgap device-based six-phase permanent magnet synchronous machine (PMSM) drives. The presence of low-order harmonics is common in the back EMF of PMSMs with low slot and high pole numbers. The back EMF harmonics generate low-order harmonic currents that increase torque ripples. Furthermore, zero-sequence current (ZSC) is also observed if all six phases are connected to a common neutral point. ZSC does not affect the torque ripple but reduces the system efficiency. A special technique is required to reduce ZSC for variable speed drives as direct ac component to synchronous reference frame (SRF) dc transformation is not possible for ZSC. In this article, a voltage injection-based current harmonics reduction method is proposed. The injected harmonic voltage coefficients are calculated from the harmonic estimations of back EMF and updated using closed-loop harmonic compensators to improve steady-state performance. For ZSC reduction, third harmonics power controller, and for 6n ± 1 (n = 1, 2,...) order harmonic current reduction, SRF current controllers are presented in this article. Furthermore, the current harmonics minimization method is experimentally verified using a GaN-based three-level active neutral point clamped inverter-driven six-phase PMSM.

42 ENGINEERING↗

Digital Correlation Microwave Polarimetry: Analysis and Demonstration

The design, analysis, and demonstration of a digital-correlation microwave polarimeter for use in earth remote sensing is presented. We begin with an analysis of three-level digital correlation and develop the correlator transfer function and radiometric sensitivity. A fifth-order polynomial regression is derived for inverting the digital correlation coefficient into the analog statistic. In addition, the effects of quantizer threshold asymmetry and hysteresis are discussed. A two-look unpolarized calibration scheme is developed for identifying correlation offsets. The developed theory and calibration method are verified using a 10.7 GHz and a 37.0 GHz polarimeter. The polarimeters are based upon 1-GS/s three-level digital correlators and measure the first three Stokes parameters. Through experiment, the radiometric sensitivity is shown to approach the theoretical as derived earlier in the paper and the two-look unpolarized calibration method is successfully compared with results using a polarimetric scheme. Finally, sample data from an aircraft experiment demonstrates that the polarimeter is highly-useful for ocean wind-vector measurement.

Piepmeier, J. R.↗