Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “test vector”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1980

Test vectors development and optimization for a microprocessor

This paper describes a method for generating and optimizing test vectors for a microprocessor, with the aid of a fault simulator implemented entirely by hardware. The development and optimization of test vectors has been done on a tester, with the fault simulator plugged directly into the test head. The fault simulator is capable of automatically injecting over a thousand single or multiple stuck faults in the sequential and combinatorial parts of the microprocessor. The test vectors developed by a programmer working interactively with the tester were applied through the tester to the fault simulator, and the percent of faults detected was measured. The vectors were developed and optimized for the 1802 microprocessor, with the objective of detecting 100% of the single stuck faults with a minimum set of vectors. Experimental results show that 99.7% of the single stuck faults are being detected with approximately 14,000 vectors.

Timoc, C. C.↗
NASA NTRS1980

MIL-M-38510/470 test vectors: Fault detection efficiency measurement via hardware fault simulation

The stuck fault detection efficiency of the test vectors developed for the MIL-M-38510/470 NASA was measured using a hardware stuck fault simulator for the 1802 microprocessor. Thirty-nine stuck faults were not detected out of a total of 874 injected into the combinatorial and sequential parts of the microprocessor. Since undetected faults can create catastrophic errors in equipment designed for high reliability applications, it is recommended that the MIL-M-38510/470 NASA be enhanced with additional test vectors so as to achieve 100% stuck fault detection efficiency.

Timoc, C. C.↗
NASA NTRS2019

Terminal Area Test Vector Development

This presentation provides an overview of work being done to develop test vectors for the terminal area, in coordination with RTCA Special Committee 228, an organization developing the Minimum Operational Performance Standards (MOPS) for Unmanned Aircraft Systems (UAS) Detect and Avoid (DAA) systems. The work leverages existing encounter data to develop a set of encounters to be used to define and refine both performance-based and functionally-based terminal area MOPS requirements. The encounter set would be used across various organizations supporting MOPS terminal area requirements development to provide some level of consistency in terms of terminal area assumptions. The work will investigate other potentially applicable data sets and make any similarly needed adjustments to arrive at a consolidated set of terminal area encounters.

terminal area↗
NASA NTRS1984

Hardware Fault Simulator Generates Test Vectors For Complex IC's

Report describes technique using fault simulator implemented entirely in hardware to generate and optimize test vectors for microprocessor. Hardware fault simulator approach reduces test time, while maintaining high reliability in detecting faults.

Timoc, C. C.↗
DOE OSTI2024

Test Vector Development for Verification and Validation of Heavy-Duty Autonomous Vehicle Operations

The current focus in the ongoing development of autonomous driving systems (ADS) for heavy duty vehicles is that of vehicle operational safety. To this end, developers and researchers alike are working towards a complete understanding of the operating environments and conditions that autonomous vehicles are subject to during their mission. This understanding is critical to the testing and validation phases of the development of autonomous vehicles and allows for the identification of both the nominal and edge case scenarios encountered by these systems. Previous work by the authors saw the development of a comprehensive scenario generation framework to identify an operating domain specification (ODS), or external and internal conditions an autonomous driving system can expect to encounter on its mission to form critical scenario groups for autonomous vehicle testing and validating using statistical patterns, clustering, and correlation. Continuing this prior work, this paper focuses on the generation of test cases based on the critical scenarios identified that can be used to prioritize either the most common nominal driving scenarios or the least common severe driving scenarios. These test cases can then be used validate, through simulation or real-world testing, the operating design domain (ODD) for a generalized driving mission and built upon to identify spatial and temporal impacts on the driving mission of an autonomous vehicle.

Siekmann, Adam↗
NASA NTRS2019

TAO Test Vector Evaluation Rev. 1

A group of encounter sets is evaluated as a standard for defining and refining both performance-based and functional-based terminal area MOPS requirements. DAIDALUS-alerting is used together with a variety of sensor configurations: (1) ADS-B level surveillance, (2) TCAS II, (3) ground-based RADAR with three different sets of error parameters.

Adami, Tony↗
NASA NTRS1989

Test aspects of the JPL Viterbi decoder

The generation of test vectors and design-for-test aspects of the Jet Propulsion Laboratory (JPL) Very Large Scale Integration (VLSI) Viterbi decoder chip is discussed. Each processor integrated circuit (IC) contains over 20,000 gates. To achieve a high degree of testability, a scan architecture is employed. The logic has been partitioned so that very few test vectors are required to test the entire chip. In addition, since several blocks of logic are replicated numerous times on this chip, test vectors need only be generated for each block, rather than for the entire circuit. These unique blocks of logic have been identified and test sets generated for them. The approach employed for testing was to use pseudo-exhaustive test vectors whenever feasible. That is, each cone of logid is tested exhaustively. Using this approach, no detailed logic design or fault model is required. All faults which modify the function of a block of combinational logic are detected, such as all irredundant single and multiple stuck-at faults.

Breuer, M. A.↗
NASA NTRS1988

A fault injection experiment using the AIRLAB Diagnostic Emulation Facility

The preparation for, conduct of, and results of a simulation based fault injection experiment conducted using the AIRLAB Diagnostic Emulation facilities is described. An objective of this experiment was to determine the effectiveness of the diagnostic self-test sequences used to uncover latent faults in a logic network providing the key fault tolerance features for a flight control computer. Another objective was to develop methods, tools, and techniques for conducting the experiment. More than 1600 faults were injected into a logic gate level model of the Data Communicator/Interstage (C/I). For each fault injected, diagnostic self-test sequences consisting of over 300 test vectors were supplied to the C/I model as inputs. For each test vector within a test sequence, the outputs from the C/I model were compared to the outputs of a fault free C/I. If the outputs differed, the fault was considered detectable for the given test vector. These results were then analyzed to determine the effectiveness of some test sequences. The results established coverage of selt-test diagnostics, identified areas in the C/I logic where the tests did not locate faults, and suggest fault latency reduction opportunities.

Baker, Robert↗
DOE OSTI2026

Accelerating multigrid with streaming chiral SVD for Wilson fermions in lattice QCD

A modification to the setup algorithm for the multigrid preconditioner of Wilson fermions in lattice QCD is presented. A larger basis of test vectors than that used in regular multigrid is calculated by the smoother and truncated by singular value decomposition on the chiral components of the test vectors. The truncated basis is used to form the prolongation and restriction matrices of the multigrid hierarchy. This modification of the setup method is demonstrated to increase the convergence of linear solvers on an anisotropic lattice with m π ≈ 239 MeV from the Hadron Spectrum Collaboration and an isotropic lattice with m π ≈ 220 MeV from the MILC Collaboration. The lattice volume dependence of the method is also examined. Increasing the number of test vectors improves speedup up to a point, but storing these vectors becomes impossible in limited memory resources such as GPUs. To address storage cost, we implement a streaming singular value decomposition of the basis of test vectors on the chiral components and demonstrate a decrease in the number of fine level iterations by a factor of 1.7 for m q ≈ m crit

Iterative methods↗
DOE OSTI2025

Chiral rank-$k$ truncations for the multigrid preconditioner of Wilson fermions in lattice QCD

We present a modification to the setup algorithm for the multigrid preconditioner of Wilson fermions in lattice QCD. A larger number of test vectors than that used in conventional multigrid is generated by the smoother. This set of test vectors is then truncated by a singular value decomposition on the chiral components of the test vectors, which are subsequently used to form the prolongation and restriction matrices of the multigrid hierarchy. This modification is demonstrated to improve the convergence of linear equations on an anisotropic lattice with 𝑚𝜋 ≈ 280 MeV from the Hadron Spectrum Collaboration and an isotropic lattice with 𝑚𝜋 ≈ 220 MeV from the MILC Collaboration. The lattice volume dependence of the method is also examined.

Whyte, Travis [Jülich Supercomputing Center, Jülic↗
NASA NTRS1993

Fluidic scale model multi-plane thrust vector control test results

An experimental investigation has been conducted at the NASA Langley 16-Foot Transonic Tunnel Static Test Facility to determine the concept feasibility of using fluidics to achieve multiplane thrust vector control in a 2D convergent-divergent (2D-CD) fixed aperture nozzle. Pitch thrust vector control is achieved by injection of flow through a slot in the divergent flap into the primary nozzle flow stream. Yaw vector control results from secondary air delivered tangentially to vertical Coanda flaps. These flaps are offset laterally and aligned parallel to the primary nozzle side walls. All tests were conducted at static (no external flow) conditions. Flow visualization was conducted using a paint flow technique and Focus Schlieren. Significant levels of pitch deflection angles (19 deg) were achieved at low pressure ratios and practical levels (14 deg) resulted at typical intermediate power settings. The ability of the Coanda surface blowing concept to produce yaw deflection was limited to NPR not greater than 4.

Chiarelli, Charles↗
DOE OSTI2015

A complementation assay for in vivo protein structure/function analysis in Physcomitrella patens (Funariaceae)

Premise of the study: A method for rapid in vivo functional analysis of engineered proteins was developed using Physcomitrella patens . Methods and Results: A complementation assay was designed for testing structure/function relationships in cellulose synthase (CESA) proteins. The components of the assay include (1) construction of test vectors that drive expression of epitope‐tagged PpCESA5 carrying engineered mutations, (2) transformation of a ppcesa5 knockout line that fails to produce gametophores with test and control vectors, (3) scoring the stable transformants for gametophore production, (4) statistical analysis comparing complementation rates for test vectors to positive and negative control vectors, and (5) analysis of transgenic protein expression by Western blotting. The assay distinguished mutations that generate fully functional, nonfunctional, and partially functional proteins. Conclusions: Compared with existing methods for in vivo testing of protein function, this complementation assay provides a rapid method for investigating protein structure/function relationships in plants.

59 BASIC BIOLOGICAL SCIENCES↗
NASA NTRS1981

Failure detection and isolation analysis of a redundant strapdown inertial measurement unit

The objective of this study was to define and develop techniques for failure detection and isolation (FDI) algorithms for a dual fail/operational redundant strapdown inertial navigation system are defined and developed. The FDI techniques chosen include provisions for hard and soft failure detection in the context of flight control and navigation. Analyses were done to determine error detection and switching levels for the inertial navigation system, which is intended for a conventional takeoff or landing (CTOL) operating environment. In addition, investigations of false alarms and missed alarms were included for the FDI techniques developed, along with the analyses of filters to be used in conjunction with FDI processing. Two specific FDI algorithms were compared: the generalized likelihood test and the edge vector test. A deterministic digital computer simulation was used to compare and evaluate the algorithms and FDI systems.

Motyka, P.↗
NASA NTRS1984

Segmented testing

The fraction of faults detected for a digital network is frequently high for the first few input combinations applied out of a set of test vectors. When the particular ordering of test patterns does not appreciably change the shape of the coverage curve, there appears to be an advantage to splitting the test into segments which are applied at different times. It is shown that the expected time to error detection and the probability of an undetected double error can be reduced. The amount of reduction is dependent on the shape of the fault coverage curve. It is conjectured that such a reduction can be obtained for VLSI networks.

Robinson, J. P.↗
NASA NTRS1985

Segmented testing

The fraction of faults detected for a digital network is frequently high for the first few input combinations applied out of a set of test vectors. When the particular ordering of test patterns does not appreciably change the shape of the coverage curve, there appears to be an advantage to splitting the test into segments which are applied at different times. It is shown that the expected time to error detection and the probability of an undetected double error can be reduced. The amount of reduction is dependent on the shape of the fault coverage curve. It is conjectured that such a reduction can be obtained for VLSI networks.

Robinson, J. P.↗