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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Three influential factors on colloidal nanoparticle deposition for heat conduction enhancement in 3D chip stacks

Thermal management is one of the major challenges facing the development of three-dimensional (3D) chip stacks. Recently, experimental studies have shown that neck-based thermal structure (NTS) between chip layers formed by drying of colloidal suspension in cavity filled with micro-size particles can improve the vertical heat conduction threefold. However, a deep understanding of the mechanisms of neck formation and its influence on heat conduction is still lacking. In this paper, we numerically study the effects of three parameters, i.e., initial nanoparticle concentration, drying temperature and chip surface wettability on neck formation between filler particles and on the resulting heat conduction of the NTS. With increasing nanoparticle concentration, the size and number of necks increase, resulting in an increased effective thermal conductivity (ETC) of NTS. The drying temperature is found to have only little influence on the ETC of resultant NTS, while the neck size and spatial distribution become more uniform at higher drying temperature. When reducing the wettability of the top and bottom surfaces of the cavity, the necks shrink in size until completing evacuating at the top and bottom layers, while the size of the necks between filler particles in the middle height of the cavity expands slowly. In consequence, the ETC of NTS drops at an increasing rate. Being able to reveal the underlying multiple mechanisms of two-phase flow, phase change and heat transport, the current numerical study suggests optimal values for the deposition process, with initial nanoparticle concentration over 0.8%, a drying temperature of 60°C and a uniform contact angle of 30° for practical production of NTS.

3D chip stacks↗
DOE OSTI2022

A novel hardmask-to-substrate pattern transfer method for creating 3D, multi-level, hierarchical, high aspect-ratio structures for applications in microfluidics and cooling technologies

Abstract This letter solves a major hurdle that mars photolithography-based fabrication of micro-mesoscale structures in silicon. Conventional photolithography is usually performed on smooth, flat wafer surfaces to lay a 2D design and subsequently etch it to create single-level features. It is, however, unable to process non-flat surfaces or already etched wafers and create more than one level in the structure. In this study, we have described a novel cleanroom-based process flow that allows for easy creation of such multi-level, hierarchical 3D structures in a substrate. This is achieved by introducing an ultra-thin sacrificial silicon dioxide hardmask layer on the substrate which is first 3D patterned via multiple rounds of lithography. This 3D pattern is then scaled vertically by a factor of 200–300 and transferred to the substrate underneath via a single shot deep etching step. The proposed method is also easily characterizable—using features of different topographies and dimensions, the etch rates and selectivities were quantified; this characterization information was later used while fabricating specific target structures. Furthermore, this study comprehensively compares the novel pattern transfer technique to already existing methods of creating multi-level structures, like grayscale lithography and chip stacking. The proposed process was found to be cheaper, faster, and easier to standardize compared to other methods—this made the overall process more reliable and repeatable. We hope it will encourage more research into hybrid structures that hold the key to dramatic performance improvements in several micro-mesoscale devices.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2025

Performance of the AstroPix Prototype Module for the Barrel Imaging Calorimeter at the ePIC Detector and in Space-Based Payloads

AstroPix is a high-voltage CMOS (HV-CMOS) monolithic active pixel sensor originally developed to enable precision gamma-ray imaging and spectroscopy in the medium-energy regime (~100 keV–100 MeV) based on the groundwork laid by ATLASpix and MuPix. It features a 500 μm pixel pitch, in-pixel amplification and digitization, and low power consumption (~3-4 mW/cm2), making it scalable for large-area, multilayer telescope detector planes. The detectors have a designed dynamic range of 25 keV to 700 keV. With these features, AstroPix meets the requirements of future space-based high-energy telescopes and the imaging layers of the Barrel Imaging Calorimeter (BIC) in the Electron-Proton/Ion Collider (ePIC) detector at the future Electron-Ion Collider (EIC). For the space-based payload, AstroPix is being integrated into sounding rocket and balloon payloads to demonstrate the technical readiness of the devices. For BIC, AstroPix-based imaging layers interleaved within the lead/scintillating-fiber (Pb/SciFi) sampling calorimeter provide granular shower imaging, enabling key performance features such as electron/pion or gamma/neutral pion separation. As part of the ongoing detector R&D efforts, we have been testing various AstroPix_v3 configurations: the single chip, a quad-chip assembly, a three-layer stack of quad chips, and a 9-chip module that represents the smallest prototype unit of the BIC imaging layer. This presentation will highlight recent performance test results from these AstroPix detector configurations.

Kim, Bobae (ORCID:0000000295396815)↗
DOE OSTI2024

Stacked-Die SiC Half-Bridge Module with Minimum Loop Inductance

Minimizing parasitic inductance of power modules is needed to advance their electrical performance. Innovation in the past decade has driven down the inductance of SiC half-bridge power modules to around 1–2 nH by using multilayer, embedded, and hybrid structures. Further reduction becomes difficult, mainly limited by the excessive interconnects required for the planar placement of vertical conducting chips. To address this, a vertically stacked-die approach is proposed in this paper, taking advantage of the vertical conducting nature of the SiC chips. With ceramic decoupling capacitors integrated, 0.48 nH overall loop inductance is achieved and validated by experimental measurement. This paper also discusses potential approaches to further reduce the inductance.

Ribeiro, Pedro↗
DOE OSTI2026

A Cryogenic Muon Tagging System Integrated with a Superconducting Qubit Device for Radiation-Induced Error Mitigation

Superconducting qubits are highly sensitive to ionizing radiation, which can induce correlated errors and limit scalable fault-tolerant quantum computing. In particular, cosmic-ray muons can deposit energy in the substrate, generating phonon bursts that break Cooper pairs and produce quasiparticles, leading to correlated decoherence events across multiple qubits. We present the development of a cryogenic muon tagging system based on Kinetic Inductance Detectors (KIDs) and its integration with superconducting quantum hardware. Originally developed within the ACE-SuperQ project and validated as a standalone detector, the system demonstrated a muon tagging efficiency of approximately 90% and excellent agreement with Monte Carlo simulations. Building on this validation, the tagging system has been integrated with a multi-qubit superconducting chip operated in a dilution refrigerator. The detector configuration consists of a multi-layer KID stack arranged above and below the quantum device, enabling time-coincident identification of muon-induced events within the same cryogenic environment. The integrated setup has been successfully commissioned, enabling simultaneous operation of the qubit chip and the muon tagging system. A first measurement campaign has been carried out, and preliminary data show time-correlated events between the muon tagging detectors and the qubit readout. A quantitative analysis of radiation-induced effects on qubit performance is currently ongoing. This work represents a step toward the implementation of event-level radiation tagging as a tool for characterizing and potentially mitigating correlated errors in superconducting quantum processors, while establishing a modular platform for future studies at the interface between particle physics and quantum information science.

Roy, Tanay [Fermilab] (ORCID:000000019442862X)↗
DOE OSTI2023

Deployment of ADTimePix3 areaDetector Driver at Neutron and X-ray User Facilities

TimePix3 is a 65k hybrid pixel readout chip with simultaneous Time-of-Arrival (ToA) and Time-over-Threshold (ToT) recording in each pixel*. The chip operates without a trigger signal with a sparse readout where only pixels containing events are read out. The flexible architecture allows 40 MHits/s/cm² readout throughput, using simultaneous readout and acquisition by sharing readout logic with transport logic of superpixel matrix formed using 2x4 structure. The chip ToA records 1.5625 ns time resolution. The X-ray and charged particle events are counted directly. However, indirect neutron counts use 6Li fission in a scintillator matrix, such as ZnS(Ag). The fission space-charge region is limited to 5-9 um. A photon from scintillator material excites a photocathode electron, which is further multiplied in dual-stack MCP. The neutron count event is a cluster of electron events at the chip. We report on the EPICS areaDetector** ADTimePix3 driver that controls Serval*** using json commands. The driver directs data to storage and to a real-time processing pipeline and configures the chip. The time-stamped data are stored in raw .tpx3 file format and passed through a socket where the clustering software identifies individual neutron events. The conventional 2D images are available as images for each exposure frame, and a preview is useful for sample alignment. The areaDetector driver allows integration of time-enhanced capabilities of this detector into SNS beamlines controls and unprecedented time resolution.

Gofron, Kaz↗
DOE OSTI2021

The upgrade of the ALICE TPC with GEMs and continuous readout

The upgrade of the ALICE TPC will allow the experiment to cope with the high interaction rates foreseen for the forthcoming Run 3 and Run 4 at the CERN LHC. In this article, we describe the design of new readout chambers and front-end electronics, which are driven by the goals of the experiment. Gas Electron Multiplier (GEM) detectors arranged in stacks containing four GEMs each, and continuous readout electronics based on the SAMPA chip, an ALICE development, are replacing the previous elements. The construction of these new elements, together with their associated quality control procedures, is explained in detail. Finally, the readout chamber and front-end electronics cards replacement, together with the commissioning of the detector prior to installation in the experimental cavern, are presented. After a nine-year period of R&D, construction, and assembly, the upgrade of the TPC was completed in 2020.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

Advanced Heterogeneous Integration Enabled by 3D Freestanding Membranes—From Material Growths to Applications

For the future of electronics such as bioelectronics, 3D integrated electronics, and bendable electronics, the need for flexibility and stackability of electronic products has substantially grown up. However, conventional wafer-based single-crystalline semiconductors cannot catch up with such trends because they are bound to thick rigid wafers such that they are neither flexible nor stackable. Although polymer-based organic electronic materials are more compatible as they are mechanically compliant and less costly than inorganic counterparts, their electronic/photonic performance is substantially inferior to that of single-crystalline inorganic materials. Such performance-mechanical compliance dilemma could be resolved by developing methods to obtain cheap, flexible, stackable, single-crystalline inorganic systems. Such dream electronic systems could be realized by producing single-crystalline freestanding membranes. For the past few decades, various layer transfer techniques (a.k.a layer liftoff techniques) have been developed to produce single-crystalline freestanding membranes. In today's talk, I will present the survey of the layer liftoff techniques and go over how these strategies unlock new ways of manufacturing advanced electronic systems. In addition, I will introduce unprecedented artificial heterostructure devices enabled by stacking of those freestanding 3D material membranes, e.g., the world's smallest vertically-stacked full-color micro-LEDs, the world's best multiferroic devices, chip-less wireless e-skin, and reconfigurable hetero-integrated chips with AI accelerators.

Kim, Jeehwan↗
DOE OSTI2022

Advanced Heterogeneous Integration Enabled by 3D Freestanding Membranes—From Material Growths to Applications

For the future of electronics such as bioelectronics, 3D integrated electronics, and bendable electronics, the need for flexibility and stackability of electronic products has substantially grown up. However, conventional wafer-based single-crystalline semiconductors cannot catch up with such trends because they are bound to thick rigid wafers such that they are neither flexible nor stackable. Although polymer-based organic electronic materials are more compatible as they are mechanically compliant and less costly than inorganic counterparts, their electronic/photonic performance is substantially inferior to that of single-crystalline inorganic materials. Such performance-mechanical compliance dilemma could be resolved by developing methods to obtain cheap, flexible, stackable, single-crystalline inorganic systems. Such dream electronic systems could be realized by producing single-crystalline freestanding membranes. For the past few decades, various layer transfer techniques (a.k.a layer liftoff techniques) have been developed to produce single-crystalline freestanding membranes. In today's talk, I will present the survey of the layer liftoff techniques and go over how these strategies unlock new ways of manufacturing advanced electronic systems. In addition, I will introduce unprecedented artificial heterostructure devices enabled by stacking of those freestanding 3D material membranes, e.g., the world's smallest vertically-stacked full-color micro-LEDs, the world's best multiferroic devices, chip-less wireless e-skin, and reconfigurable hetero-integrated chips with AI accelerators.

Kim, Jeehwan↗
DOE OSTI2020

Layer-Dependent Bit Error Variation in 3-D NAND Flash Under Ionizing Radiation

In this paper, we studied the total ionization dose (TID) effects on the multilevel-cell (MLC) 3-D NAND flash memory using Co-60 gamma radiation. We found a significant page-to-page bit error variation within a physical memory block of the irradiated memory chip. Our analysis showed that the origin of the bit error variation is the unique vertical layer-dependent TID response of the 3-D NAND. We found that the memory pages located at the upper and lower layers of the 3-D stack show higher fails compared to the middle-layer pages of a given memory block. We confirmed our findings by comparing radiation response of four different chips of the same specification. In addition, we compared the TID response of the MLC 3-D NAND with that of the 2-D NAND chip, which showed less page-to-page variation in bit error within a given memory block. We discuss the possible application of our findings for the radiation-tolerant smart memory controller design.

3-D NAND flash↗
DOE OSTI2020

Record thermopower found in an IrMn-based spintronic stack

The Seebeck effect converts thermal gradients into electricity. As an approach to power technologies in the current Internet-of-Things era, on-chip energy harvesting is highly attractive, and to be effective, demands thin film materials with large Seebeck coefficients. In spintronics, the antiferromagnetic metal IrMn has been used as the pinning layer in magnetic tunnel junctions that form building blocks for magnetic random access memories and magnetic sensors. Spin pumping experiments revealed that IrMn Néel temperature is thickness-dependent and approaches room temperature when the layer is thin. Here, we report that the Seebeck coefficient is maximum at the Néel temperature of IrMn of 0.6 to 4.0 nm in thickness in IrMn-based half magnetic tunnel junctions. We obtain a record Seebeck coefficient 390 (±10) μV K -1 at room temperature. Our results demonstrate that IrMn-based magnetic devices could harvest the heat dissipation for magnetic sensors, thus contributing to the Power-of-Things paradigm.

42 ENGINEERING↗
DOE OSTI2022

Low-temperature processed beta-phase In 2 Se 3 ferroelectric semiconductor thin film transistors

As scaling becomes increasingly difficult, there is growing interest in vertical or three-dimensional stacking of transistors and especially memory. Ferroelectric semiconductor field effect transistors can be key enablers to improve energy efficiency and overall chip and memory performance. In this work, low-temperature processed, back-end-of-the-line compatible transistors were demonstrated by depositing a layered chalcogenide ferroelectric semiconductor, beta-phase In 2 Se 3 , at temperature as low as 400 °C. Top gate n-channel In 2 Se 3 thin film transistors were fabricated with field-effect mobility ∼1 cm 2 V −1 s −1 , and simple polarization switching based memory results are presented.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Beam test performance of a prototype module with Short Strip ASICs for the CMS HL-LHC tracker upgrade

The Short Strip ASIC (SSA) is one of the four front-end chips designed for the upgrade of the CMS Outer Tracker for the High Luminosity LHC. Together with the Macro-Pixel ASIC (MPA) it will instrument modules containing a strip and a macro-pixel sensor stacked on top of each other. The SSA provides both full readout of the strip hit information when triggered, and, together with the MPA, correlated clusters called stubs from the two sensors for use by the CMS Level-1 (L1) trigger system. Results from the first prototype module consisting of a sensor and two SSA chips are presented. The prototype module has been characterized at the Fermilab Test Beam Facility using a 120 GeV proton beam.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

Enabling Highly Efficient Capsule Networks Processing Through A PIM-Based Architecture Design

In recent years, the CNNs have achieved great successes in the image processing tasks, e.g., image recognition and object detection. Unfortunately, traditional CNN's classication is found to be easily misled by increasingly complex image features due to the usage of pooling operations, hence unable to preserve accurate position and pose information of the objects. To address this challenge, a novel neural network structure called Capsule Network has been proposed, which introduces equivariance through capsules to signicantly enhance the learning ability for image segmentation and object detection. Due to its requirement of performing a high volume of matrix operations, CapsNets have been generally accelerated on modern GPU platforms that provide highly optimized software library for common deep learning tasks. However, based on our performance characterization on modern GPUs, CapsNets exhibit low effciency due to the special program and execution features of their routing procedure, including massive unshareable intermediate variables and intensive syn- chronizations, which are very dicult to optimize at software level. To address these challenges, we propose a hybrid computing architecture design named PIM-CapsNet. It preserves GPU's on-chip computing capability for accelerating CNN types of layers in CapsNet, while pipelining with an off-chip in-memory acceleration solution that effectively tackles routing procedure's ineffciency by leveraging the processing-in-memory capability of today's 3D stacked memory. Using routing procedure's inherent parallellization feature, our design enables hierarchical improvements on CapsNet inference effciency through minimizing data movement and maximizing parallel processing in memory. Evaluation results demonstrate that our proposed design can achieve substantial improvement on both performance and energy savings for CapsNet inference, with almost zero accuracy loss. The results also suggest good performance scalability in optimizing the routing procedure with increasing network size.

Zhang, Xingyao↗
DOE OSTI2021

Influence of side-chain isomerization on the isothermal crystallization kinetics of poly(3-alkylthiophenes)

Flexible alkyl side chain in conjugate polymers (CPs) improves the solubility and promotes solution processability, in addition, it affects interchain packing and charge mobilities. Despite the well-known charge mobility and morphology correlation for these semi-crystalline polymers, there is a lack of fundamental understanding of the impact of side chain on their crystallization kinetics. In the present work, isothermal crystallization of five poly(3-alkylthiophene-2,5-diyl) (P3ATs) with different side-chain structures were systematically investigated. To suppress the extremely fast crystallization and trap the sample into amorphous glass, an advanced fast scanning chip calorimetry technique, which is able to quench the sample with few to tens thousands of K/s, was applied. Results show that the crystallization of P3ATs was greatly inhibited after incorporation of branched side chains, as indicated by a dramatic up to six orders of magnitude decrease in the crystallization rate. The suppressed crystallization of P3ATs were correlated with an increased π–π stacking distance due to unfavorable side-chain steric interaction. This research provides a pathway to use side-chain engineering to control the crystallization behavior for CPs, thus to control device performance.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Giant Nonlinear Optical Response via Coherent Stacking of In-Plane Ferroelectric Layers

Thin ferroelectric materials hold great promise for compact nonvolatile memory and nonlinear optical and optoelectronic devices. Herein, an ultrathin in-plane ferroelectric material that exhibits a giant nonlinear optical effect, group-IV monochalcogenide SnSe, is reported. Nanometer-scale ferroelectric domains with ≈90°/270° twin boundaries or ≈180° domain walls are revealed in physical-vapor-deposited SnSe by lateral piezoresponse force microscopy. Atomic structure characterization reveals both parallel and antiparallel stacking of neighboring van der Waals ferroelectric layers, leading to ferroelectric or antiferroelectric ordering. Ferroelectric domains exhibit giant nonlinear optical activity due to coherent enhancement of second-harmonic fields and the as-resulted second-harmonic generation was observed to be 100 times more intense than monolayer WS 2 . This work demonstrates in-plane ferroelectric ordering and giant nonlinear optical activity in SnSe, which paves the way for applications in on-chip nonlinear optical components and nonvolatile memory devices.

36 MATERIALS SCIENCE↗