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Availability of board level solder joint reliability information is critical to the acceptance of CSPs as alternative packages. This paper will review different CSPs as well as their assembly reliability.
Highly reliable soldered joints for printed circuit boards
Over the years, many analytical and experimental research studies have aimed to improve the state-of-the-art assessment of solder joint integrity from a physics-of-failure perspective. Although much progress has been made, there still exist many inconsistent and even contradictory correlations and conclusions. Before discussing some of the prominent inconsistencies found in the literature, this paper reviews the fundamental physics underlying the nature of solder failure...Using the complex constitutive properties of solder, fundamental mechanical and thermomechanical proccesses can be modeled to demonstrate some of the inconsistencies in the literature.
Reliability evaluation and environmental testing of printed-wiring-board soldered joints
Current and future space and defense systems face potential risks from the continued use of tin-lead solder, including: compliance with current environmental regulations, concerns about potential environmental legislation banning lead-containing products, reduced mission readiness, and component obsolescence with lead surface finishes. For example, the United States Environmental Protection Agency (USEPA) has lowered the Toxic Chemical Release reporting threshold for lead to 100 pounds. Overseas, the Waste Electrical and Electronic Equipment (WEEE) and the Restriction on Hazardous Substances (RoHS) Dicctives in Europe and similar mandates in Japan have instilled concern that a legislative body will prohibit the use of lead in aerospace/military electronics soldering. Any potential banning of lead compounds could reduce the supplier base and adversely affect the readiness of missions led by the National Aeronautics and Space Administration (NASA) and the U.S. Department of Defense (DoD). Before considering lead-free electronics for system upgrades or future designs, however, it is important for the DoD and NASA to know whether lead-free solders can meet their systems' requirements. No single lead-free solder is likely to qualify for all defense and space applications. Therefore, it is important to validate alternative solders for discrete applications. As a result of the need for comprehensive test data on the reliability of lead-free solders, a partnership was formed between the DoD, NASA, and several original equipment manufactures (OEMs) to conduct solder-joint reliability (laboratory) testing of three lead-free solder alloys on newly manufactured and reworked circuit cards to generate performance data for high-reliability (IPC Class 3) applications.
Availability of board solder joint reliability information is critical to the wider implementation of Chip Scale Packages (CSPs).
Availability of board solder joint reliability information is critical to the wider implementation of Chip Scale Packages (CSPs).
Availability of board solder joint reliability information is critical to the wider implementation of Chip Scale Packages (CSPs).
JPL, in a partnership with an industrial consortium, is currently engaged in the investigation of reliability and quality issues if ball grid array (BGA) packages as they may be applied to space flight electronics. Performing tests to determine the solder joint reliability of assemblies using BGAs under temperature cycling has proved to be a real challenge for test engineers.
For five decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in miniaturization of electronics products-Moore's Law. Now, scaling hits a brick wall, a paradigm shift. The industry roadmaps recognized the scaling limitation and project that packaging technologies will meet further miniaturization needs or ak.a "More than Moore". This paper presents packaging technology trends and accelerated reliability testing methods currently being practiced. Then, it presents industry status on key advanced electronic packages, factors affecting accelerated solder joint reliability of area array packages, and IPC/JEDEC/Mil specifications for characterizations of assemblies under accelerated thermal and mechanical loading. Finally, it presents an examples demonstrating how Accelerated Testing and Analysis have been effectively employed in the development of complex spacecraft thereby reducing risk. Quantitative assessments necessarily involve the mathematics of probability and statistics. In addition, accelerated tests need to be designed which consider the desired risk posture and schedule for particular project. Such assessments relieve risks without imposing additional costs. and constraints that are not value added for a particular mission. Furthermore, in the course of development of complex systems, variances and defects will inevitably present themselves and require a decision concerning their disposition, necessitating quantitative assessments. In summary, this paper presents a comprehensive view point, from technology to systems, including the benefits and impact of accelerated testing in offsetting risk.
Electronics, without requiring heater power or enclosure in a centralized 'warm electronics box,' will need to survive mean surface temperatures of -120 degrees Celsius to +20 degrees Celsius for an extended Martian mission and an operational temperature up to 85 degrees Celsisus. Since these electronics will need to survive extended cycles under these conditions, fatigue is a significant concern. The solder joint reliability of connectors on a printed wiring board was investigated.
The overall objective of the Hex Chrome Free Coatings for Electronics project is to evaluate and test pretreatment coating systems not containing hexavalent chrome in avionics and electronics housing applications. This objective will be accomplished by testing strong performing coating systems from prior NASA and DoD testing or new coating systems as determined by the stakeholders. The technical stakeholders have agreed that this protocol will focus specifically on Class 3 coatings. Original Equipment Manufacturers (OEMs), depots, and support contractors have to be prepared to deal with an electronics supply chain that increasingly provides parts with lead-free finishes, some labeled no differently and intermingled with their SnPb counterparts. Allowance of lead-free components presents one of the greatest risks to the reliability of military and aerospace electronics. The introduction of components with lead-free terminations, termination finishes, or circuit boards presents a host of concerns to customers, suppliers, and maintainers of aerospace and military electronic systems such as: 1. Electrical shorting due to tin whiskers 2. Incompatibility of lead-free processes and parameters (including higher melting points of lead-free alloys) with other materials in the system 3. Unknown material properties and incompatibilities that could reduce solder joint reliability
Investigation of parallel gap soldering of electrical leads resulted in recommendation on material preparation, equipment, process control, and visual inspection criteria to ensure reliable solder joints. The recommendations will minimize problems in heat-dwell time, amount of solder, bridging conductors, and damage of circuitry.
While the electronics industry appears to be focusing on Sn-Ag-Cu as the alloy of choice for lead free electronics assembly, ,the exact composition varies by geographic region, supplier and user. Add to that dissolved copper and silver from the printed circuit board traces and surface finish, and there can be significant variation in the final solder joint composition. A systematic study of the mechanical and microstructural properties of Sn-Ag-Cu alloys with Ag varying from 2wt% to 4wt% and Cu varying from 0.5wt% to lSwt%, was undertaken in this research study. Different sample preparation techniques (water quenched, oil quenched and water quenched followed by reflow) were explored and the resulting microstructure compared to that of a typical reflowed lead free chip scale package (CSP) solder joint. Tensile properties (modulus, 0.2% yield strength and the ultimate tensile strength) and creep behavior of selected alloy compositions (Sn-4Ag-1 X u , Sn-4Ag-OSCu, Sn- 2Ag-1 X u , Sn-2Ag-OSCu, Sn-3.5Ag-O.SCu) were determined for three conditions: as- cast; aged for 100 hours at 125OC; and aged for 250 hours at 125OC. There was no significant difference in Young's Modulus as a function of alloy composition. After an initial decrease in modulus after 100 hours at 125"C, there was an insignificant change with further aging. The distribution of 0.2% strain yield stress and ultimate tensile strength as a function of alloy composition was more significant and decreased with aging time and temperature. The microstructures of these alloys were examined using light and scanning electron microscopy (LM and SEM) respectively and SEM based energy dispersive x-ray spectroscopy (EDS). Fracture surface and cross-section analysis were performed on the specimens after creep testing. The creep testing results and the effect of high temperature aging on mechanical properties is presented for the oil quenched samples. In general the microstructure of oil quenched specimen exhibited a eutectic region of Sn with moderately dispersed Ag3Sn intermetallic, surrounded by a dendritic Sn-rich phase. The SEM images of the fracture surface indicated the presence of a tough shear surface at the initial cavity break area and a break line in the middle of specimen along the failure direction. A hyperbolic-sine creep model was adopted and used to fit the creep experiment data. The effect on the mechanical properties by adding the quaternary element bismuth to the Sn-3.5Ag-0.8Cu alloy was measured and compared with the mechanical properties of the ternary alloys. The results of this research study provide necessary data for the modeling of solder joint reliability for a range of Sn-Ag-Cu compositions and a baseline for evaluating the effects of subsequent quaternary additions.
A 472 dimpled ball grid array (D-BGA) package has not been used in past space flight environments, therefore it was necessary to develop a process that would yield robust and reliable solder joints. The process developing assembly, inspection and rework techniques, were verified by conducting environmental tests. Since the 472 D-BGA packages passed the above environmental tests within the specifications, the process was successfully developed for space flight electronics.
Spacecraft electronics including those used at the Jet Propulsion Laboratory (JPL), demand production of highly reliable assemblies. JPL has recently completed an extensive study, funded by NASA's code Q, of the interplay between manufacturing defects and reliability of ball grid array (BGA) and surface mount electronic components.
Spacecraft electronics as used in the NASA community, including the Jet Propulsion Laboratory.
No abstract provided