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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Liveness as a factor to evaluate memory vulnerability to soft errors

Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. In some cases, memory faults can be diagnosed by redundant execution and a diagnostic coverage may be determined.

Bramley, Richard Gavin↗
NASA NTRS2000

Scaling and technology issues for soft error rates

Th effects of device technology and scaling on soft error rates are discussed, using information obtained from both the device and space communities as a guide to determine the net effect on soft errors.

soft error rate space radiation high-energy proton↗
NASA NTRS1989

Total dose effect on soft error rate for dynamic metal-oxide-semiconductor memory cells

A simple model for the soft error rate for dynamic metal-oxide-semiconductor random access memories due to normal galactic radiation was devised and then used to calculate the rate of decrease of the single-event-upset rate with total radiation dose. The computation shows that the decrease in the soft error rate is less than 10 percent per day if the shielding is 0.5 g/sq cm and the spacecraft is in a geosynchronous orbit. The decrease is considerably less in a polar orbiting device.

Benumof, Reuben↗
NASA NTRS1979

Simulation of cosmic-ray induced soft errors and latchup in integrated-circuit computer memories

Soft errors have been induced in solid-state static RAM's by iron nuclei from the Lawrence Berkeley Laboratory (LBL) Bevalac, in experiments designed to prove the ability of iron-group cosmic rays to generate such errors. Subsequently, various delidded device types were tested in beams of argon and krypton ions from the LBL 88-inch Cyclotron, at energies near 2 MeV/nucleon. The latter tests showed that some devices are essentially immune to bit error while others are quite susceptible. Good agreement was obtained with model predictions in cases where the latter exist. Latchup, whose cause is attributed to individual heavy ions, was also observed in some device types.

Kolasinski, W. A.↗
NASA NTRS1979

Cosmic ray-induced soft errors in static MOS memory cells

Previous analytical models were extended to predict cosmic ray-induced soft error rates in static MOS memory devices. The effect is due to ionization and can be introduced by high energy, heavy ion components of the galactic environment. The results indicate that the sensitivity of memory cells is directly related to the density of the particular MOS technology which determines the node capacitance values. Hence, CMOS is less sensitive than e.g., PMOS. In addition, static MOS memory cells are less sensitive than dynamic ones due to differences in the mechanisms of storing bits. The flip-flop of a static cell is inherently stable against cosmic ray-induced bit flips. Predicted error rates on a CMOS RAM and a PMOS shift register are in general agreement with previous spacecraft flight data.

Sivo, L. L.↗
NASA NTRS1984

Soft-error generation due to heavy-ion tracks in bipolar integrated circuits

Both bipolar and MOS integrated circuits have been empirically demonstrated to be susceptible to single-particle soft-error generation, commonly referred to as single-event upset (SEU), which is manifested in a bit-flip in a latch-circuit construction. Here, the intrinsic characteristics of SEU in bipolar (static) RAM's are demonstrated through results obtained from the modeling of this effect using computer circuit-simulation techniques. It is shown that as the dimensions of the devices decrease, the critical charge required to cause SEU decreases in proportion to the device cross-section. The overall results of the simulations are applicable to most integrated circuit designs.

Zoutendyk, J. A.↗
NASA NTRS2010

Impact of Spacecraft Shielding on Direct Ionization Soft Error Rates for sub-130 nm Technologies

We use ray tracing software to model various levels of spacecraft shielding complexity and energy deposition pulse height analysis to study how it affects the direct ionization soft error rate of microelectronic components in space. The analysis incorporates the galactic cosmic ray background, trapped proton, and solar heavy ion environments as well as the October 1989 and July 2000 solar particle events.

Pellish, Jonathan A.↗
NASA NTRS2010

Impact of Spacecraft Shielding on Direct Ionization Soft Error Rates for Sub-130 nm Technologies

We use ray tracing software to model various levels of spacecraft shielding complexity and energy deposition pulse height analysis to study how it affects the direct ionization soft error rate of microelectronic components in space. The analysis incorporates the galactic cosmic ray background, trapped proton, and solar heavy ion environments as well as the October 1989 and July 2000 solar particle events.

Pellish, Jonathan A.↗
NASA NTRS1990

Asymmetric Memory Circuit Would Resist Soft Errors

Some nonlinear error-correcting codes more efficient in presence of asymmetry. Combination of circuit-design and coding concepts expected to make integrated-circuit random-access memories more resistant to "soft" errors (temporary bit errors, also called "single-event upsets" due to ionizing radiation). Integrated circuit of new type made deliberately more susceptible to one kind of bit error than to other, and associated error-correcting code adapted to exploit this asymmetry in error probabilities.

Buehler, Martin G.↗
NASA NTRS1985

Modeling "Soft" Errors in Bipolar Integrated Circuits

Mathematical models represent single-event upset in bipolar memory chips. Physics of single-event upset in integrated circuits discussed in theoretical paper. Pair of companion reports present mathematical models to predict critical charges for producing single-event upset in bipolar randomaccess memory (RAM) chips.

Zoutendyk, J.↗
NASA NTRS1984

Bipolar junction transistor models for circuit simulation of cosmic-ray-induced soft errors

This paper examines bipolar junction transistor models suitable for calculating the effects of large excursions of some of the variables determining the operation of a transistor. Both the Ebers-Moll and Gummel-Poon models are studied, and the junction and diffusion capacitances are evaluated on the basis of the latter model. The most interesting result of this analysis is that a bipolar junction transistor when struck by a cosmic particle may cause a single event upset in an electronic circuit if the transistor is operated at a low forward base-emitter bias.

Benumof, R.↗
NASA NTRS1991

Asymmetric soft-error resistant memory

A memory system is provided, of the type that includes an error-correcting circuit that detects and corrects, that more efficiently utilizes the capacity of a memory formed of groups of binary cells whose states can be inadvertently switched by ionizing radiation. Each memory cell has an asymmetric geometry, so that ionizing radiation causes a significantly greater probability of errors in one state than in the opposite state (e.g., an erroneous switch from '1' to '0' is far more likely than a switch from '0' to'1'. An asymmetric error correcting coding circuit can be used with the asymmetric memory cells, which requires fewer bits than an efficient symmetric error correcting code.

Buehler, Martin G.↗