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In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.
Methods of manufacturing a semiconductor device, and resulting semiconductor device are described. In an example, the method for manufacturing a semiconductor device include forming a semiconductor region and forming a metal seed region over the semiconductor region. The method can include placing a conductive strip over a first portion of the metal region, where the conductive strip is formed over the semiconductor region. The method can include bonding a contacting portion of the conductive strip to the first portion the metal region. The method can include etching a second portion of the metal region and where the conductive strip inhibits etching of the first portion of the metal region. In an example, the conductive strip can have a coating. In one example, the semiconductor device can be a solar cell.
A method for predicting failure parameters of semiconductor devices can include receiving a set of data that includes (i) characteristics of a sample semiconductor device, and (ii) parameters characterizing a stress condition. The method further includes extracting a plurality of feature values from the set of data and inputting the plurality of feature values into a trained model executing on the one or more processors, wherein the trained model is configured according to an artificial intelligence (AI) algorithm based on a previous plurality of feature values, and wherein the trained model is operable to output a failure prediction based on the plurality of feature values. Further, the method includes generating, via the trained model, a predicted failure parameter of the sample semiconductor device due to the stress condition.
Systems and methods for organic semiconductor devices with sputtered contact layers are provided. In one embodiment, an organic semiconductor device comprises: a first contact layer comprising a first sputter-deposited transparent conducting oxide; an electron transport layer interfacing with the first contact layer; a second contact layer comprising a second sputter-deposited transparent conducting oxide; a hole transport layer interfacing with the second contact layer; and an organic semiconductor active layer having a first side facing the electron transport layer and an opposing second side facing the hole transport layer; wherein either the electron transport layer or the hole transport layer comprises a buffering transport layer.
Systems and methods for organic semiconductor devices with sputtered contact layers are provided. In one embodiment, an organic semiconductor device comprises: a first contact layer comprising a first sputter-deposited transparent conducting oxide; an electron transport layer interfacing with the first contact layer; a second contact layer comprising a second sputter-deposited transparent conducting oxide; a hole transport layer interfacing with the second contact layer; and an organic semiconductor active layer having a first side facing the electron transport layer and an opposing second side facing the hole transport layer; wherein either the electron transport layer or the hole transport layer comprises a buffering transport layer.
Systems and methods for organic semiconductor devices with sputtered contact layers are provided. In one embodiment, an organic semiconductor device comprises: a first contact layer (140) comprising a first sputter-deposited transparent conducting oxide; an electron transport layer (130) interfacing with the first contact layer; a second contact layer (110) comprising a second sputter-deposited transparent conducting oxide; a hole transport layer interfacing with the second contact layer; and an organic semiconductor active layer (120) having a first side facing the electron transport layer and an opposing second side facing the hole transport layer; wherein either the electron transport layer or the hole transport layer comprises a buffering transport layer.
In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.
This paper presents a unique approach to enable real-time lifespan prediction of semiconductor power modules using a Hardware-in-the-Loop (HIL) system. By integrating the module's overall loss characteristics-specifically switching and conduction losses-with a thermoelectric model of the thermal management system, this research demonstrates that the model can dynamically estimates the junction temperature profile of the semiconductor devices in response to a changing torque demand profile for the motor drive system. This capability enables continuous monitoring of the module's operational time and cumulative stress induced on the devices to compute accumulated remaining lifetime or time-to-failure (TTF). This study provides an architectural framework for the HIL system with high-fidelity component models of multiple physical domains, allowing simulation of dynamic behaviors of a closely-coupled motor drive system. The advanced real-time computation and measurement functionalities of the HIL system allow for both dynamic lifetime calculations based on simulated data and aggregate lifetime predictions utilizing historical data. Moreover, this paper details an algorithm that not only computes cumulative damage but also synthesizes these data into a comprehensive aggregated lifetime metric. This methodology can enhance the maintenance scheduling strategies and operational reliability of semiconductor devices in critical applications, ultimately extending their service life while optimizing performance.
Two-dimensional (2D) perovskites have gained much attention lately owing to their excellent optoelectronic properties, chemical tunability, and environmental stability. Multiple methods have been devised to synthesize high quality 2D perovskite single crystals, and recent progress in fabricating its heterostructures is notable as well. In particular, with growing interest in 2D van der Waals heterostructures, 2D perovskites have become a strong candidate as a new building block for heterostructures to reveal unique physical properties across different interfaces. Until now, various heterostructure devices of 2D perovskite single crystals with other types of 2D materials such as transition metal dichalcogenides (TMDs) and graphene have been studied, which have shown intriguing results including interlayer excitons and enhanced electronic properties. Here, we introduce various synthetic approaches to realize 2D perovskite single crystals and unique characteristics of their single crystal heterostructures fabricated with precision, possessing sharp interfaces. Moreover, recent studies of semiconductor devices based on 2D perovskite single crystal heterostructures are discussed in-depth. New perspectives to further the horizon in the field of 2D perovskite heterostructures are suggested in this work including the consideration of metal–2D material van der Waals contact, application of dry transfer techniques, electric bias driven ion diffusion studies, and nanocrystal array fabrication. 2D perovskite heterostructure single crystal devices factoring in these novel perspectives will further uncover the true potential of these materials for highly efficient and stable semiconductor devices.
A new three-level isolated ac-dc power factor correction (PFC) topology with a minimum number of semiconductor devices is the focus of this paper. This topology provides a high input power factor (PF), soft-switching, and higher efficiency than existing isolated ac-dc converters. Furthermore, the proposed circuit has lower voltage rating requirements for the secondary side devices, which leads to a lower total cost and minimizes total converter losses. This article presents a theoretical analysis describing the complete characterization of this new topology, and experimental results on a 1-kW prototype showing high PF and efficiency throughout the operating range.
We demonstrate the ability of a relatively new analytical technique, near-zero-field magnetoresistance (NZFMR), to track atomic-scale phenomena involved in the high-field stressing damage of fully processed Si metal-oxide-semiconductor field-effect transistors. We show that the technique is sensitive to both the Pb0 and Pb1 dangling bond centers and that the presence of both centers can be inferred through NZFMR via hyperfine interactions with the central 29Si atoms of the dangling bonds. The NZFMR results also provide evidence for the redistribution of mobile hydrogen atoms at the Si/SiO2 interface and also a potential change in the average dipolar coupling constant between electrons in neighboring defects. This work shows that NZFMR offers significant analytical power for studying technologically relevant semiconductor device reliability problems and has advantages in experimental simplicity over comparable techniques.
For decades, the semiconductor technology has followed the Moore’s law, making newer devices more powerful and energy efficient. Recently, however, it has reached a point where the performance and the energy efficiency of the device do not improve with the shrinking device size. One of the fundamental reasons of this deviation from the past trend is the interconnect resistance, which becomes larger with the shrinking size. The devices size is so small that the quantum mechanical effects can no longer be ignored and the traditional continuum simulation tools such as TCAD become inadequate. In this project, Samsung Semiconductor Inc. and Lawrence Berkeley National Laboratory has collaborated to perform first of kind device-scale ab initio simulations to optimize materials and interconnect morphology to minimize interconnect resistance. We have tested the use of LS3DF method and the PEtot_trans approach on top of the folded spectrum method (FSM) Escan code to calculate the scattering state, and to study various effects influence the interconnect conductivity. We found that, the LS3DF can be used to calculate such metallic system. On the other hand, the use of Escan code to solve the linear equation is not practical due to the slow convergence. We have implemented a Chebyshev filter technique to calculate a few hundred eigen states near the scattering state energy E, then use these eigen states as preconditioner to solve the linear equation. We have used this approach to study the different factors which affect the interconnect conductivity, including the shape, the point defect, the temperature, and the grain boundary.
Dopant atoms in semiconductors can be ionized with ∼ 10 meV energy depositions, allowing for the design of low-threshold detectors. We propose using doped semiconductor targets to search for sub-MeV dark matter scattering or sub-eV dark matter absorption on electrons. Currently unconstrained cross sections could be tested with a 1 g-day exposure in a doped detector with backgrounds at the level of existing pure semiconductor detectors, but improvements would be needed to probe the freeze-in target. We discuss the corresponding technological requirements and lay out a possible detector design. Published by the American Physical Society 2024
The use of grazing-incidence scattering methods for the characterization of 2D patterned organic thin films is limited due to the elongated 1D footprint of the X-ray beam on the sample. However, this characteristic feature can be turned into an advantage, when combined with tomographic reconstruction. In this pilot study we show, how the use of a chosen texture reflection and a diffuse reflectivity signal can each provide 2D images of the deposits, simultaneously revealing the organic film's crystal orientation and the location of the metal electrodes in a field-effect transistor structure from a single sequence of diffraction images.
Nitrogen-vacancy (N-V) centers in diamond work as a quantum electrometer. Using an ensemble state of N-V centers, we propose vector electrometry and demonstrate measurements in a diamond electronic device. A transverse electric field applied to the N-V axis under a high voltage is measured, while applying a transverse magnetic field. The response of the energy-level shift against the electric field is significantly enhanced compared with that against an axial magnetic field. Repeating the measurement of the transverse electric field for multiple N-V axes, our team obtains the components of the electric field generated in the device.
GaN has electronic properties that make it an excellent material for the next generation of power electronics; however, its radiation hardening still needs further understanding before it is used in radiation environments. In this work we explored the response of commercial InGaN LEDs to two different radiation environments: ion and gamma irradiations. For ion irradiations we performed two types of irradiations at the Ion Beam Lab (IBL) at Sandia National Laboratories (SNL): high energy and end of range (EOR) irradiations. For gamma irradiations we fielded devices at the gamma irradiation facility (GIF) at SNL. The response of the LEDs to radiation was investigated by IV, light output and light output vs frequency measurements. We found that dose levels up to 500 krads do not degrade the electrical properties of the devices and that devices exposed to ion irradiations exhibit a linear and non- linear dependence with fluence for two different ranges of fluence levels. We also performed current injection annealing studies to explore the annealing properties of InGaN LEDs.
Abstract not provided.
Abstract not provided.