SEARCH · Engineering Papers
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Hydrocarbon polymer coatings used in microelectronic manufacturing processes are anisotropically etched by hyperthermal atomic oxygen beams (translational energies of 0.2 to 20 eV, preferably 1 to 10 eV). Etching with hyperthermal oxygen atom species obtains highly anisotropic etching with sharp boundaries between etched and mask protected areas.
Eliminating photolithography from solar cell processing is a significant opportunity for cost reduction for III-V solar cells. Here, in this work, we explore femtosecond laser ablation as an alternative to contact photolithography and wet chemical etching for mesa isolation. We demonstrate both GaAs and GaInP solar cells mesa-isolated by femtosecond laser ablation with minimal to no loss in solar cell performance. We show the best results with a 400 fs UV pulsed laser and a short clean-up etch that also serves as a contact layer removal etch.
To eliminate thermal fatigue, a procedure for manufacturing semiconductor power devices with pure pressure contact without solid binding was developed. Pressure contact without the use of a solid binding to avoid a limitation of the maximum surface in the contact was examined. A silicon wafer covered with a relatively thick metal layer is imbedded with the aid of a soft silver foil between two identically sized hard contact discs (molybdenum or tungsten) which are rotationally symmetrical. The advantages of this concept are shown for large diameters. The pressure contact was tested successfully in many devices in a large variety of applications.
Eliminating photolithography from photovoltaic device processing is a significant opportunity for cost reduction and increased manufacturing throughput. In this work, we test femtosecond laser ablation and scribing as an alternative to contact photolithography and wet chemical etching for mesa isolation of multijunction devices. We demonstrate that upright multijunction devices isolated by using the laser as a scribe to cleave through the substrate had virtually no performance loss when compared to a baseline device processed with photolithography. By contrast, devices isolated by laser ablating through the active layers have performance losses that cannot be fully eliminated with postprocess etching. This demonstration of photolithography-free mesa isolation with no performance losses is promising as a pathway to less expensive and higher throughput III-V device manufacturing.
Goddard Space Flight Center microelectronics program - integrated circuit block and semiconductor process development
Equations derived to estimate obscuration ratios of surfaces contaminated by particles. Ratio is fraction of surface area covered by particles. Useful as index of cleanliness in clean-room operations in manufacturing of semiconductor devices, magnetic recording media, optical devices, and pharmaceutical and biotechnological products.
A method of effecting modifications at the surfaces of materials using low energy ion beams of known quantum state, purity, flux, and energy is presented. The ion beam is obtained by bombarding ion-generating molecules with electrons which are also at low energy. The electrons used to bombard the ion generating molecules are separated from the ions thus obtained and the ion beam is directed at the material surface to be modified. Depending on the type of ion generating molecules used, different ions can be obtained for different types of surface modifications such as oxidation and diamond film formation. One area of application is in the manufacture of semiconductor devices from semiconductor wafers.
This paper presents a methodology to incorporate and analyze the impact of semiconductor device part-to-part variation on power converter performance. By integrating extensive static and dynamic device characterization data with an automated compact model generation process that reflects manufacturing variability, device models with inherent variability features are utilized in converter simulations for a comprehensive assessment of performance impacts. The traditional converter performance evaluation process typically yields fixed efficiency values, often dismissing the inherent part-to-part variability caused by the manufacturing process of semiconductor devices. To address this limitation, a large population of devices was characterized to capture variations in static parameters-such as transfer, output, and capacitance characteristics-as well as dynamic behaviors, including switching losses. This data-driven approach enables the development of individual compact models, which were then integrated into converter simulations to evaluate efficiency ranges rather than single point estimated values. The converter simulation results show that part-to-part component variation can lead to significant efficiency deviations, exceeding several percentage points in high-power conversion applications. By offering a more accurate representation of converter behavior under real-world manufacturing conditions, this methodology enables designers to anticipate performance variability, improving the robustness of power converter designs.
Etching and deposition of materials are critical steps in semiconductor processing for device manufacturing. Both etching and deposition may have isotropic and anisotropic components, due to directional sputtering and redeposition of materials, for example. Previous attempts at modeling profile evolution have used so-called "string theory" to simulate the moving solid-gas interface between the semiconductor and the plasma. One complication of this method is that extensive de-looping schemes are required at the profile corners. We will present a 2D profile evolution simulation using level set theory to model the surface. (1) By embedding the location of the interface in a field variable, the need for de-looping schemes is eliminated and profile corners are more accurately modeled. This level set profile evolution model will calculate both isotropic and anisotropic etch and deposition rates of a substrate in low pressure (10s mTorr) plasmas, considering the incident ion energy angular distribution functions and neutral fluxes. We will present etching profiles of Si substrates in Ar/Cl2 discharges for various incident ion energies and trench geometries.
Scanning electron microscope for poor metallization detection in manufacturing cycle of semiconductor devices
Material, design, and manufacturing studies to improve glass passivation of semiconductor devices
Cleanliness of manufactured parts and assemblies is a significant issue in many industries including disk drives, semiconductors, aerospace, and medical devices. Clean manufacturing requires cleanroom floor space and cleaning technology that are both expensive to own and expensive to operate. Strategies to reduce these costs are an important consideration. One strategy shown to be effective at reducing costs is to assemble parts into subassemblies and then clean the subassembly, rather than clean the individual parts first and then assemble them. One advantage is that assembly outside of the cleanroom reduces the amount of cleanroom floor space and its associated operating cost premium. A second advantage is that this strategy reduces the number of individual parts that must be cleaned prior to assembly, reducing the number of cleaning baskets, handling and, possibly, reducing the number of cleaners. The assemble then clean strategy also results in a part that is significantly cleaner because contamination generated during the assembly steps are more effectively removed that normally can be achieved by hand wiping after assembly in the cleanroom.
Large scale manufacture of phosphide based semiconductor devices by organo-metallic vapor phase epitaxy (OMVPE) typically requires the use of highly toxic phosphine. Advancements in phosphine substitutes have identified tertiarybutylphosphine (TBP) as an excellent precursor for OMVPE of InP. High quality undoped and doped InP films were grown using TBP and trimethylindium. Impurity doped InP films were achieved utilizing diethylzinc and silane for p and n type respectively. 16 percent efficient solar cells under air mass zero, one sun intensity were demonstrated with Voc of 871 mV and fill factor of 82.6 percent. It was shown that TBP could replace phosphine, without adversely affecting device quality, in OMVPE deposition of InP thus significantly reducing toxic gas exposure risk.
A strategy for "Solid-State" Nuclear Power is proposed to guide development of technologies and systems into the second 50 years of nuclear spaceflight. The strategy emphasizes a simple and highly integrated system architecture with few moving parts or fluid loops; the leverage of modern advances in materials, manufacturing, semiconductors, microelectromechanical and nanotechnology devices; and the targeted advancement of high temperature nuclear fuels, materials and static power conversion to enable high performance from simple system topologies.
Quantum dots in SiGe/Si/SiGe heterostructures host coherent electron spin qubits, which are promising for future quantum computers. The silicon quantum well hosts near-degenerate electron valley states, creating a low-lying excited state that is known to reduce spin qubit readout and control fidelity. The valley energy splitting is dominated by the microscopic disorder in the SiGe alloy and at the Si/SiGe interfaces, and while Si devices are compatible with large-scale semiconductor manufacturing, achieving a uniformly large valley splitting energy across a many-qubit device spanning mesoscopic distances is an outstanding challenge. In this work we study valley splitting variations in a 1D quantum dot array, formed in a Si 0.972 Ge 0.028 quantum well, manufactured by Intel. We observe correlations in valley splitting, at both sub-100 nm (single gate) and > 1 μm (device) lengthscales, that are consistent with alloy disorder-dominated theory and simulation. Our results develop the mesoscopic understanding of Si/SiGe heterostructures necessary for scalable device design.
The phrase, "common-layered architecture for semiconductor silicon carbide" ("CLASSiC") denotes a method of batch fabrication of microelectromechanical and semiconductor devices from bulk silicon carbide. CLASSiC is the latest in a series of related methods developed in recent years in continuing efforts to standardize SiC-fabrication processes. CLASSiC encompasses both institutional and technological innovations that can be exploited separately or in combination to make the manufacture of SiC devices more economical. Examples of such devices are piezoresistive pressure sensors, strain gauges, vibration sensors, and turbulence-intensity sensors for use in harsh environments (e.g., high-temperature, high-pressure, corrosive atmospheres). The institutional innovation is to manufacture devices for different customers (individuals, companies, and/or other entities) simultaneously in the same batch. This innovation is based on utilization of the capability for fabrication, on the same substrate, of multiple SiC devices having different functionalities (see figure). Multiple customers can purchase shares of the area on the same substrate, each customer s share being apportioned according to the customer s production-volume requirement. This makes it possible for multiple customers to share costs in a common foundry, so that the capital equipment cost per customer in the inherently low-volume SiC-product market can be reduced significantly. One of the technological innovations is a five-mask process that is based on an established set of process design rules. The rules provide for standardization of the fabrication process, yet are flexible enough to enable multiple customers to lay out masks for their portions of the SiC substrate to provide for simultaneous batch fabrication of their various devices. In a related prior method, denoted multi-user fabrication in silicon carbide (MUSiC), the fabrication process is based largely on surface micromachining of poly SiC. However, in MUSiC one cannot exploit the superior sensing, thermomechanical, and electrical properties of single-crystal 6H-SiC or 4H-SiC. As a complement to MUSiC, the CLASSiC five-mask process can be utilized to fabricate multiple devices in bulk single-crystal SiC of any polytype. The five-mask process makes fabrication less complex because it eliminates the need for large-area deposition and removal of sacrificial material. Other innovations in CLASSiC pertain to selective etching of indium tin oxide and aluminum in connection with multilayer metallization. One major characteristic of bulk micromachined microelectromechanical devices is the presence of three-dimensional (3D) structures. Any 3D recesses that already exist at a given step in a fabrication process usually make it difficult to apply a planar coat of photoresist for metallization and other subsequent process steps. To overcome this difficulty, the CLASSiC process includes a reversal of part of the conventional flow: Metallization is performed before the recesses are etched.
Magnetite is a common conductive mineral found on Earth and Mars. Disk-shaped precipitates approximately 40 nm in diameter have been shown to have manganese and aluminum concentrations. Atom-probe field-ion microscopy (APFIM) is the only technique that can potentially quantify the composition of these precipitates. APFIM will be used to characterize geological and planetary materials, analyze samples of interest for geomicrobiology; and, for the metrology of nanoscale instrumentation. Prior to APFIM sample preparation was conducted by electropolishing, the method of sharp shards (MSS), or Bosch process (deep reactive ion etching) with focused ion beam (FIB) milling as a final step. However, new methods are required for difficult samples. Many materials are not easily fabricated using electropolishing, MSS, or the Bosch process, FIB milling is slow and expensive, and wet chemistry and the reactive ion etching are typically limited to Si and other semiconductors. APFIM sample preparation using the dicing saw is commonly used to section semiconductor wafers into individual devices following manufacture. The dicing saw is a time-effective method for preparing high aspect ratio posts of poorly conducting materials. Femtosecond laser micromachining is also suitable for preparation of posts. FIB time required is reduced by about a factor of 10 and multi-tip specimens can easily be fabricated using the dicing saw.
Tested devices were manufactured by Semtech and Micro Semiconductor. Failure rate of Semtech diodes exceeded 50% in all three test groups. Failure mode could not be precisely determined.