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Results for “semiconductor device fabrication”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1994

Optical processing for semiconductor device fabrication

A new technique for semiconductor device processing is described that uses optical energy to produce local heating/melting in the vicinity of a preselected interface of the device. This process, called optical processing, invokes assistance of photons to enhance interface reactions such as diffusion and melting, as compared to the use of thermal heating alone. Optical processing is performed in a 'cold wall' furnace, and requires considerably lower energies than furnace or rapid thermal annealing. This technique can produce some device structures with unique properties that cannot be produced by conventional thermal processing. Some applications of optical processing involving semiconductor-metal interfaces are described.

Sopori, Bhushan L.↗
NASA NTRS1995

Method for fabricating semiconductor devices

A process for fabricating gold/gallium arsenide structures, in situ, on molecular beam epitaxially grown gallium arsenide. The resulting interface proves to be Ohmic, an unexpected result which is interpreted in terms of increased electrode interdiffusion. More importantly, the present invention surprisingly permits the fabrication of Ohmic contacts in a III-V semiconductor material at room temperature. Although it may be desireable to heat the Ohmic contact to a temperature of, for example, 200 degrees Centigrade if one wishes to further decrease the resistance of the contact, such low temperature annealing is much less likely to have any deleterious affect on the underlying substrate. The use of the term in situ herein, contemplates continuously maintaining an ultra-high vacuum, that is a vacuum which is at least 10.sup.-8 Torr, until after the metallization has been completed. An alternative embodiment of the present invention comprising an additional step, namely the termination of the gallium arsenide by a two monolayer thickness of epitaxial aluminum arsenide as a diffusion barrier, enables the recovery of Schottky barrier behavior, namely a rectified I-V characteristic. The present invention provides a significant breakthrough in the fabrication of III-V semiconductor devices wherein excellent Ohmic contact and Schottky barrier interfaces to such devices can be achieved simply and inexpensively and without requiring the high temperature processing of the prior art and also without requiring the use of exotic high temperature refractory materials as substitutes for those preferred contact metals such as gold, aluminum and the like.

Kaiser, William J.↗
NASA NTRS1993

Demonstration of Y1Ba2Cu3O(7-delta) and complementary metal-oxide-semiconductor device fabrication on the same sapphire substrate

We report the first fabrication of active semiconductor and high-temperature superconducting devices on the same substrate. Test structures of complementary MOS transistors were fabricated on the same sapphire substrate as test structures of Y1Ba2Cu3O(7-delta) flux-flow transistors, and separately, Y1Ba2Cu3O(7-delta) superconducting quantum interference devices utilizing both biepitaxial and step-edge Josephson junctions. Both semiconductor and superconductor devices were operated at 77 K. The cofabrication of devices using these disparate yet complementary electronic technologies on the same substrate opens the door for the fabrication of true semiconductive/superconductive hybrid integrated circuits capable of exploiting the best features of each of these technologies.

Burns, M. J.↗
NASA NTRS1990

Silicon carbide semiconductor device fabrication and characterization

A number of basic building blocks i.e., rectifying and ohmic contacts, implanted junctions, MOS capacitors, pnpn diodes and devices, such as, MESFETs on both alpha and beta SiC films were fabricated and characterized. Gold forms a rectifying contact on beta SiC. Since Au contacts degrade at high temperatures, these are not considered to be suitable for high temperature device applications. However, it was possible to utilize Au contact diodes for electrically characterizing SiC films. Preliminary work indicates that sputtered Pt or Pt/Si contacts on beta SiC films are someways superior to Au contacts. Sputtered Pt layers on alpha SiC films form excellent rectifying contacts, whereas Ni layers following anneal at approximately 1050 C provide an ohmic contact. It has demonstrated that ion implantation of Al in substrates held at 550 C can be successfully employed for the fabrication of rectifying junction diodes. Feasibility of fabricating pnpn diodes and platinum gated MESFETs on alpha SiC films was also demonstrated.

Davis, R. F.↗
NASA NTRS1991

Advances in silicon carbide Chemical Vapor Deposition (CVD) for semiconductor device fabrication

Improved SiC chemical vapor deposition films of both 3C and 6H polytypes were grown on vicinal (0001) 6H-SiC wafers cut from single-crystal boules. These films were produced from silane and propane in hydrogen at one atmosphere at a temperature of 1725 K. Among the more important factors which affected the structure and morphology of the grown films were the tilt angle of the substrate, the polarity of the growth surface, and the pregrowth surface treatment of the substrate. With proper pregrowth surface treatment, 6H films were grown on 6H substrates with tilt angles as small as 0.1 degrees. In addition, 3C could be induced to grow within selected regions on a 6H substrate. The polarity of the substrate was a large factor in the incorporation of dopants during epitaxial growth. A new growth model is discussed which explains the control of SiC polytype in epitaxial growth on vicinal (0001) SiC substrates.

Powell, J. Anthony↗
NASA NTRS2009

Zinc Alloys for the Fabrication of Semiconductor Devices

ZnBeO and ZnCdSeO alloys have been disclosed as materials for the improvement in performance, function, and capability of semiconductor devices. The alloys can be used alone or in combination to form active photonic layers that can emit over a range of wavelength values. Materials with both larger and smaller band gaps would allow for the fabrication of semiconductor heterostructures that have increased function in the ultraviolet (UV) region of the spectrum. ZnO is a wide band-gap material possessing good radiation-resistance properties. It is desirable to modify the energy band gap of ZnO to smaller values than that for ZnO and to larger values than that for ZnO for use in semiconductor devices. A material with band gap energy larger than that of ZnO would allow for the emission at shorter wavelengths for LED (light emitting diode) and LD (laser diode) devices, while a material with band gap energy smaller than that of ZnO would allow for emission at longer wavelengths for LED and LD devices. The amount of Be in the ZnBeO alloy system can be varied to increase the energy bandgap of ZnO to values larger than that of ZnO. The amount of Cd and Se in the ZnCdSeO alloy system can be varied to decrease the energy band gap of ZnO to values smaller than that of ZnO. Each alloy formed can be undoped or can be p-type doped using selected dopant elements, or can be n-type doped using selected dopant elements. The layers and structures formed with both the ZnBeO and ZnCdSeO semiconductor alloys - including undoped, p-type-doped, and n-type-doped types - can be used for fabricating photonic and electronic semiconductor devices for use in photonic and electronic applications. These devices can be used in LEDs, LDs, FETs (field effect transistors), PN junctions, PIN junctions, Schottky barrier diodes, UV detectors and transmitters, and transistors and transparent transistors. They also can be used in applications for lightemitting display, backlighting for displays, UV and visible transmitters and detectors, high-frequency radar, biomedical imaging, chemical compound identification, molecular identification and structure, gas sensors, imaging systems, and for the fundamental studies of atoms, molecules, gases, vapors, and solids.

Ryu, Yungryel↗
NASA NTRS1993

Chemical Vapor Deposition Of Silicon Carbide

Large single-crystal SiC boules from which wafers of large area cut now being produced commerically. Availability of wafers opens door for development of SiC semiconductor devices. Recently developed chemical vapor deposition (CVD) process produces thin single-crystal SiC films on SiC wafers. Essential step in sequence of steps used to fabricate semiconductor devices. Further development required for specific devices. Some potential high-temperature applications include sensors and control electronics for advanced turbine engines and automobile engines, power electronics for electromechanical actuators for advanced aircraft and for space power systems, and equipment used in drilling of deep wells. High-frequency applications include communication systems, high-speed computers, and microwave power transistors. High-radiation applications include sensors and controls for nuclear reactors.

Powell, J. Anthony↗
NASA NTRS2001

On the Fabrication and Behavior of Diamond Microelectromechanical Sensors (DMEMS)

CVD (chemically vapor deposited) diamond films can be processed similar to "conventional" semiconductor device fabrication and as such can be used to achieve microelectromechanical structures (MEMS) also similar to, for example, silicon technology. Very small cantilever beams, membranes, stripes, tips, etc. can be constructed in doped and undoped diamond films and offer an array of choices in diamond with its known superior properties such as elastic modulus, high temperature semiconduction, high thermal conductivity, very low coefficient of expansion and numerous other diamond parameters. This paper will review the construction and behavior of the second generation DMEMS devices comprised as an accelerometer with a diamond diaphragm for use in very high G applications and a diamond pressure sensor for very high temperature and frequency response.

Holmes, K.↗
DOE OSTI2024

A strategy to eliminate selenium oxide islands formed on the ZnSe/GaAs epilayer

Atomically clean and smooth surfaces are essential for semiconductor device fabrication and epitaxial regrowth. In this regard, spontaneously formed oxide islands or clusters on the surfaces of II-VI semiconductor exposures to air can disrupt interface formation. Using ZnSe/GaAs heterostructures grown by molecular beam epitaxy (MBE), we investigated the effect of surface treatments in eliminating oxide islands. The samples were probed with atomic force microscopy, low-temperature photoluminescence, and scanning electron microscopy. Here, it was found that ultra-high vacuum (UHV) annealing at 200°C, regardless of annealing duration, largely removed the islands while leaving the crystallinity of the ZnSe and GaAs epilayers unaffected. UHV annealing at higher temperatures of 300°C completely removed the islands, but the optical properties of ZnSe and/or GaAs epilayers deteriorated depending on the annealing duration. Our observations provide guidance to set thermal annealing strategies for removing oxide islands from the surfaces of II-VI/III-V semiconductor heterostructures depending on the desired properties.

36 MATERIALS SCIENCE↗
NASA NTRS1995

Sub-ppb Oxygen Contaminant Detection in Semi-Conductor Processing

Gaseous contaminants such as oxygen, water vapor, nitrogen and hydrocarbons are often present in the processing environment in semiconductor device fabrication and in containerless materials processing. The contaminants arise as a result of outgassing from hot surfaces or they may be part of the impurities in commercial ultra-high purity gases. Among these gaseous contaminants, oxygen is the most reactive and, therefore, has the most adverse effects on the end product. There has been an intense effort at the Jet Propulsion Laboratory to develop different types of oxygen sorbents to reduce oxygen concentration in a microgravity processing environment to sub-ppb (parts-per-billion) levels. Higher concentrations can lead to rapid surface oxide formation, hence reducing the quality of semiconductor devices. If the concentration of oxygen in a processing chamber at 1000oC is in the ppb level, it will only take approximately 10 seconds for an oxide layer to form on the surface of a sample. The interaction of oxygen with the water surface can lead to the formation of localized defects in semi-conductor devices, hence decreasing the manufacturing yield. For example, efficient production of 64 Mb RAM chips requires contaminations below ppb levels. This paper describes a technique for measuring trace quantities of oxygen contaminants by recording the monoatomic negative ions, O-, using mass spectrometry. The O- formation from the e--O2 interaction utilizes the electron dissociative attachment method that is greatly enhanced at the resonant energy (6.8 eV). The device combines a small gridded electron ionizer with a compact mass spectrometer. The concentrations of oxygen have been measured using the method of standard additions by diluting O2 in N2. The lowest detection limit obtained was 1.2 kHz (O- count rate) at a concentration of 10-10, corresponding to 0.1 ppb.

Sub-ppb Contaminant↗
DOE OSTI2023

High-throughput manufacturing of epitaxial membranes from a single wafer by 2D materials-based layer transfer process

Layer transfer techniques have been extensively explored for semiconductor device fabrication as a path to reduce costs and to form heterogeneously integrated devices. These techniques entail isolating epitaxial layers from an expensive donor wafer to form freestanding membranes. However, current layer transfer processes are still low-throughput and too expensive to be commercially suitable. Here we report a high-throughput layer transfer technique that can produce multiple compound semiconductor membranes from a single wafer. We directly grow two-dimensional (2D) materials on III–N and III–V substrates using epitaxy tools, which enables a scheme comprised of multiple alternating layers of 2D materials and epilayers that can be formed by a single growth run. Each epilayer in the multistack structure is then harvested by layer-by-layer mechanical exfoliation, producing multiple freestanding membranes from a single wafer without involving time-consuming processes such as sacrificial layer etching or wafer polishing. Moreover, atomic-precision exfoliation at the 2D interface allows for the recycling of the wafers for subsequent membrane production, with the potential for greatly reducing the manufacturing cost.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2020

Surface photovoltage spectroscopy observes junctions and carrier separation in gallium nitride nanowire arrays for overall water-splitting

Gallium nitride (GaN) nanowire arrays on silicon are able to drive the overall water-splitting reaction with up to 3.3% solar-to-hydrogen efficiency. Photochemical charge separation is key to the operation of these devices, but details are difficult to observe experimentally because of the number of components and interfaces. Here, we use surface photovoltage spectroscopy to study charge transfer in i-, n-, and p-GaN nanowire arrays on n+ -Si wafers in the presence and absence of Rh/Cr 2 O 3 co-catalysts. The effect of the space charge layer and sub-bandgap defects on majority and minority carrier transport can be clearly observed, and estimates of the built-in potential of the junctions can be made. Transient illumination of the p-GaN/n + -Si junction generates up to -1.4 V surface photovoltage by carrier separation along the GaN nanowire axis. This process is central to the overall water-splitting function of the n + -Si/p-GaN/Rh/Cr 2 O 3 nanowire array. Overall, these results improve our understanding of photochemical charge transfer and separation in group III–V semiconductor nanostructures for the conversion of solar energy into fuels.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2022

Pit rim decomposition into multiple quantum dots on surfaces of epitaxial thin films grown on pit-patterned substrates

Here, we report results of dynamical simulations according to an experimentally validated surface morphological evolution model on the formation of regular arrays of quantum dot molecules (QDMs) consisting of 1D arrays of smaller interacting quantum dots (QDs). These QD arrays form along the sides of each pit rim on the surface of a coherently strained thin film epitaxially deposited on a semiconductor substrate, the surface of which consists of a periodic pattern of inverted prismatic pits with rectangular pit openings. We find that this complex QDM pattern results from the decomposition of the pit rim from a “quantum fortress” with four elongated QDs into four 1D arrays of multiple smaller QDs arranged along each side of the pit rim. Systematic parametric analysis indicates that varying the pit opening dimensions and the pit wall inclination directly impacts the number of QDs in the resulting QDM pattern, while varying the pit depth only affects the dimensions of the QDs in the nanostructure pattern. Therefore, the number, arrangement, and sizes of QDs in the resulting pattern of QDMs on the film surface can be engineered precisely by proper tuning of the pit design parameters. Our simulation results are supported by predictions of morphological stability analysis, which explains the pit rim decomposition into multiple QDs as the outcome of a tip-splitting instability and provides a fundamental characterization of the post-instability nanostructure pattern. Our theoretical findings can play a vital role in designing optimal semiconductor surface patterns toward enabling future nanofabrication technologies.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Controlled Dielectric Breakdown to Form Pinhole Passivating Contacts

This contribution explores an alternate route to forming pinhole-based poly-Si/dielectric/c-Si passivating contacts. The method utilizes controlled dielectric breakdown or electroforming to produce nanoscale pinholes in a thick (non-tunnelling) dielectric which, when annealed, allows dopant atoms to pass from doped poly-Si through the pinholes and into the c-Si wafer, forming conductive pathways. We show that the pinholes lose passivation after electroforming but can be repassivated with a forming gas anneal. N-type contacts show contact resistivities of ~20 mOhm-cm2, but p-type contacts are ~100 mOhm-cm2. Devices show a distinct kink in the J-V curve indicative of a barrier to transport. The method can be expanded to optimized dielectric passivation stacks (not just thin, single layers) and can be formed in parallel over the faces of the wafer in selected areas (pinholes only under the grid lines).

CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SU↗
DOE OSTI2024

Dislocation half-loop control for optimal V-defect density in GaN-based light emitting diodes

V-defects are morphological defects that typically form on threading dislocations during epitaxial growth of $(0001)$-oriented GaN layers. A V-defect is a hexagonal pyramid-shaped depression with six {$10\bar{1}1$}-oriented sidewalls. These semipolar sidewalls have a lower polarization barrier than the polarization barriers present between the polar c-plane quantum wells and quantum barriers and can laterally inject carriers directly into quantum wells in GaN-based light emitting diodes (LEDs). This is especially important, as the high polarization field in c-plane GaN is a significant factor in the high forward voltage of GaN LEDs. The optimal V-defect density for efficient lateral carrier injection in a GaN LED (∼10 9 cm −2 ) is typically an order of magnitude higher than the threading dislocation density of GaN grown on patterned sapphire substrates (∼10 8 cm −2 ). Pure-edge dislocation loops have been known to exist in GaN, and their formation into large V-defects via low-temperature growth with high Si-doping has recently been studied. Here, in this work, we develop a method for pure-edge threading dislocation half-loop formation and density control via disilane flow, growth temperature, and thickness of the half-loop generation layer. We also develop a method of forming the threading dislocation half-loops into V-defects of comparable size to those originating from substrate threading dislocations.

Crystallographic defects↗
DOE OSTI2022

Gallium Nitride Superjunction Transistor (Continued Funding Report)

The initial goal of this project is to develop the gallium vacancy assisted diffusion (GAID) method in GaN and apply it to demonstrate 2-terminal, 3-terminal, and large area Superjunction-enhanced modules. These devices will find use in high efficiency power conversion applications with the capability of operating at higher voltages, higher frequency, and less loss than comparable stat-ofthe-art devices. The approach of this project has been to utilize simulation tools to drive diffusion experiments and inform semiconductor device fabrication processes. VASP has been relied upon to simulate first principles diffusion mechanisms while SILVACO TCAD has been utilized to understand tradeoffs of the the critical dimensions in GaN devices.

42 ENGINEERING↗
DOE OSTI2023

Synthetic Metal Atomic Layer Deposition Tool (Final Report)

As part of the Cyclotron Road program, Laminera Inc. worked towards development of atomic layer deposition process customizations and tool modifications to produce synthetic metal films at commercial scale and improve the film quality. Today's state-of-the-art in atomic layer deposited synthetic metal technology is only possible at a research-scale because current tools have practical limitations for scaling industrially and generating high conductivity films. Ultrathin, conformal synthetic metal films have many possible applications such as high surface area nanoporous electrodes for supercapacitors and water desalination devices; protective electrode coatings for electrochemical devices; seed layers for semiconductor device fabrication; or metallic component stabilizing coatings that enable enhanced storage density in next generation hard disk drives. The best synthetic metal conductive and plasmonic properties have been demonstrated using sputtering, which relies on high temperature sputtering with substrate dependent and directional growth limiting usage. This work explored refining process and tool modifications to create ultrathin, conformal, synthetic metal films that can be deposited with high quality over complex three-dimensional surfaces.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Modeling and Design of Micro Flux Monitors for Neutron Fluence Measurements

Measuring neutron flux is critical to understanding the characteristics of nuclear reactors and can provide information on the energy spectrum, total neutron fluence, and operational history of a facility. Such measurements are typically performed by irradiating high-purity materials in an operating reactor for a known length of time. By measuring and identifying activation products in the irradiated materials and referencing the energy-dependent cross section of each isotope, the neutron energy spectrum and total fluence can be determined. Historical techniques use a variety of small, individually pressed foils or wires for dosimeter devices, which can result in excessively high levels of radioactivity and complications in handling after irradiation. The present work describes a new neutron dosimetry concept, named the micro flux monitor, that uses semiconductor device fabrication processes to deposit thin films of flux monitoring materials in precise geometries onto a SiC wafer. This approach allows multiple dosimetry materials to be located on a single device, simplifying irradiation and subsequent analysis. The geometry, and therefore mass, of each material can be custom-tailored for a specific application—considering the expected neutron flux, duration of irradiation, and device retrieval time of a facility. Additionally, hundreds of identical dosimetry monitors can be produced simultaneously, reducing fabrication costs. Finally, the extremely thin metal dimensions of these devices could improve the fidelity of neutron fluence measurements by reducing neutron self-shielding and gamma self-attenuation effects.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗