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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Optimization and Performance Characterization of the Second Generation Fermilab Constant Fraction Discriminator Readout ASIC

We present the optimization and performance characterization of the second-generation Fermilab Constant Fraction Discriminator ASIC (FCFD), designed for the readout of AC-coupled low-gain avalanche detector (LGAD) strip-sensors. The FCFD is explicitly engineered to be insensitive to signal-amplitude variations, thereby removing the need for time-walk correction that is required in other LGAD time-stamping readout ASICs. This updated version, referred to as FCFD1.1, incorporates several enhancements over the first iteration to address key challenges in AC-coupled LGAD front-end design. We outline the primary readout-ASIC design considerations for these applications, describe the methodology used to evaluate critical sensor and system parameters, and summarize the additionally implemented features. Performance measurements using injected charge signals and minimum-ionizing particles in test-beams demonstrate a time resolution of approximately 40 ps and a position resolution of roughly \SI{15}{\micro\meter} when tested with beam particles uniformly over the active area of the sensor.

Apresyan, Artur [Fermilab] (ORCID:0000000261860130↗
DOE OSTI2023

A 32-channels readout ASIC for X-ray spectrometry and tracking in the GAPS experiment

Here this work describes the architecture and the experimental results from the characterization of a 32-channels mixed-signal Application-Specific Integrated Circuit (ASIC) developed for the readout of the lithium-drifted silicon, Si(Li), detectors of the General AntiParticle Spectrometer (GAPS) experiment dedicated to searching for dark matter. The instrument is designed for the identification of antiprotons, antideuterons and antihelium nuclei from cosmic rays during an Antarctic balloon mission scheduled for late 2024. A full custom integrated circuit, named SLIDER32 (32-channels Si-LI DEtector Readout) ASIC, has been produced in a commercial 180 nm CMOS technology. The ASIC is comprised of 32 low-noise analog readout channels featuring dynamic signal compression to comply with the wide input range, an 11-bit SAR ADC and a digital back-end section which is responsible for channel setting and for sending digital information to the data acquisition system (DAQ). The circuit design criteria and the experimental results are discussed in the paper.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Reusable Verification Components for High-Energy Physics readout ASICs

Verification is a critical aspect of designing front-end (FE) readout ASICs for High-Energy Physics (HEP) experiments. These ASICs share several similar functional features, resulting in similar verification objectives, which can be addressed using comparable verification strategies. This contribution presents a set of re-usable verification components for addressing common verification tasks, such as clock generation, reset handling, configuration, as well as hit and fault injections. The components were developed as part of the CHIPS initiative and they have been successfully used in the verification of multiple HEP ASICs.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2026

Versatile High-Gain Low-Noise Readout ASIC for Silicon Microstrip Tracking Detectors

This work presents Turpial, a custom-designed low- power front-end readout ASIC for microstrip silicon sensors. Implemented in 130 nm CMOS technology, the chip integrates 64 identical readout channels, each including a configurable charge-sensitive amplifier, a bipolar pulse shaper, a 32-sample 50 Msps analog memory, and a 12-bit RC-hybrid SAR ADC operating at 1 Msps. To satisfy the target power budget of 5 mW per channel, the architecture employs a time-decoupled readout scheme in which fast transient signals are first captured in the analog memory and subsequently digitized at a lower rate. Turpial supports a wide dynamic range from 1 kℎ+ to 1 Mℎ+ while maintaining low noise performance, targeting an equivalent noise charge (ENC) below 200 𝑒−including the sensor, and providing a maximum gain of 1500 mV/fC. A digital block manages slow control, data acquisition, and data serialization through dual CML 300 Mb/s serializers. In addition, an on-chip reference circuit, based on a sub-1 V bandgap reference and an integrated LDO regulator, eliminates the need for external reference circuitry. Experimental results demonstrate that both the individual building blocks and the fully integrated ASIC meet the design specifications.

Hernandez, Hugo [Stanford University] (ORCID:00000↗
DOE OSTI2025

GRAPH — an readout ASIC for large MCP based detectors

We present a programmable 16 channel, mixed signal, low power readout ASIC, having the project historically named Gigasample Recorder of Analog waveforms from a PHotodetector (GRAPH). It is designed to read large aperture single photon imaging detectors using micro channel plates for charge multiplication, and measuring the detector's response on crossed strips anodes to extrapolate the incoming photon position. Each channel consists of a fast, low power and low noise charge sensitive amplifier, which provides a myriad of coarse and fine programmable options for gain and shaping settings. Further, the amplified signal is recorded using, to our knowledge novel, the Hybrid Universal sampLing Architecture (HULA) ADC. A kind of mixed signal double buffer memory, that enables concurrent waveform recording, and selected event digitized data extraction. The sampling frequency is freely adjustable between few kHz up to 125 MHz, while the chip's internal digital memory holds a history 2048 samples for each channel, with a digital headroom of 12 bits. An optimized region of interest sample-read algorithm allows to extract the information just around the event pulse peak, while selecting the next event, thus substantially reducing the operational dead time. The chip is designed in 130 nm TSMC CMOS technology, and its power consumption is around 47 mW per channel.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

Radiation-Hard Smart-Pixel Detector ASIC ReadOut with Digital AI in 28nm

Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. This effort is pursuing the co-design development of high-performance readout smart pixel ASICs for a future Phase III High Luminosity upgrade of the Large Hadron Collider. A 1.6mm2 ASIC prototype was designed by Fermilab in CMOS 28 nm bulk process and submitted for manufacturing in February 2024. It leverages the analog front-end pixel design of a previous prototype fabricated and tested in 2023, which achieved a simulated detection level of ~400e- with 30fF input capacitance. The ROIC consists of two matrices of 16×16 smart pixels, each 25×25 μm2 in size. Each smart pixel contains a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. There is digital space for the integration of our fully combinatorial AI that performs momentum classification at the bunch crossing rate. The total power consumption is ∼6μW per pixel, which corresponds to ~1mW/cm2. The ASIC incorporates programmable front-end charge injection circuitry to generate pixel cluster charges during characterization. The cluster profile will be generated to duplicate hit characteristics of various momentum (pT). We will present early results from chip testing.

Parpillon, Benjamin↗
DOE OSTI2023

A Sub-Electron-Noise Multi-Channel Cryogenic Skipper-CCD Readout ASIC

The MIDNA application specific integrated circuit (ASIC) is a skipper-CCD readout chip fabricated in a 65 nm LP-CMOS process that is capable of working at cryogenic temperatures. The chip integrates four front-end channels that process the skipper-CCD signal and performs differential averaging using a dual slope integration (DSI) circuit. Each readout channel contains a pre-amplifier, a DC restorer, and a dual-slope integrator with chopping capability. The integrator chopping is a key system design element in order to mitigate the effect of low-frequency noise produced by the integrator itself, and it is not often required with standard CCDs. Each channel consumes 4.5 mW of power, occupies 0.156 mm${^2}$ area and has an input referred noise of 2.7${\mu\nu}_{rms}$. It is demonstrated experimentally to achieve sub-electron noise when coupled with a skipper-CCD by means of averaging samples of each pixel. Here, sub-electron noise is shown in three different acquisition approaches. The signal range is 6000 electrons. The readout system achieves 0.2${e^{-}}$ RMS by averaging 1000 samples with MIDNA both at room temperature and at 180 Kelvin.

1/f noise↗
DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗
DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗
NASA NTRS2012

ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

Vasile, Stefan↗
DOE OSTI2025

Improved Charge Sensing on a SiMOS Double Quantum Dot using a Cryogenic Skipper Readout ASIC (Quandarum)

Major outstanding questions in high-energy physics such as the nature of dark matter and the existence of interactions beyond the standard model require new measurement techniques which are extremely sensitive to minute electromagnetic fields. An array of entangled spin qubits is a promising system for building novel detectors due to its combination of sensitivity and controllability. CMOS-based electron spin qubits, which have demonstrated the operational requirements for fault-tolerant quantum computing [1], offer a particular opportunity due to their compatibility with classical electronics, which allows the leveraging of decades of development of low-noise cryogenic detectors for physics. In this work, we combine a SiMOS double-quantum dot device architecture with a state-of-the-art cryoelectronic readout circuit [2-3] aimed to demonstrate improved charge readout using a single-electron transistor (SET). We identify the design characteristics for an SET that facilitate the use of on-chip classical electronics as a low-power, high-bandwidth first amplification stage and explore opportunities for sensor-readout co-design to minimize noise. This is the first of a series of steps to demonstrate high-fidelity readout of a large array of spin qubit with enough sensitivity to probe processes of interest for the investigation of beyond-standard-model physics.

Quinn, Adam [Fermilab]↗
DOE OSTI2026

Characterization of high-flux cadmium zinc telluride detectors coupled to MM-PAD readout ASICs for high-flux X-ray applications

High-flux cadmium zinc telluride (HF-CZT) is a promising material for next-generation X-ray imaging due to its high stopping power, wide bandgap, and improved resistance to radiation-induced polarization [1]. We bonded 2 mm thick HF-CZT sensors with Cornell's Mixed-Mode Pixel Array ASICs, which combine analog charge integration and in-pixel digital counting to achieve single X-ray sensitivity, large full well capacity, and frame rates up to 10 kHz [2,3]. Detector characterization showed stable electron collection above 150 V bias, while hole collection remained limited by trapping even at 700 V. Temporal studies revealed non-negligible afterglow, with an unexpected increase in afterglow at higher biases, which was reduced by infrared illumination, suggesting that injected carriers reduce trapping near contact interfaces. Polarization measurements confirmed improved stability compared to conventional CZT, though polarization effects persisted, particularly with hole collection, with up to 5% signal loss and spatial distortion at high doses.

36 MATERIALS SCIENCE↗
NASA NTRS2014

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

radiation hardened by design↗
DOE OSTI2022

Highly Segmented Silicon Strip Detectors for Radiation Detection (LDRD Final Report)

Large area highly segmented silicon strip detectors were investigated for use in applied radiation detection applications. Two ASIC-based readout electronics solutions were tested for compatibility. During the analysis, it was determined that significant computational resources and highly specialized firmware are required to reconstruct the data into a meaningful data stream for generalized spectroscopic performance. Future investment in the technology and careful choice of readout ASIC is expected to demonstrate relevance in measuring high activity samples.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗