Workmanship Risks: Reworking Printed Circuit Board (PCB) Solder Joints
No abstract available
Plante, Jeannette↗
SEARCH · Engineering Papers
Results for “printed circuit board (PCB)”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Demonstrating the Effect of Particle Impact Dampers on the Random Vibration Response and Fatigue Life of Printed Wiring Assemblies
In a recent experimental study, small Particle Impact Dampers (PID) were bonded directly to the surface of printed circuit board (PCB) or printed wiring assemblies (PWA), reducing the random vibration response and increasing the fatigue life. This study provides data verifying practicality of this approach. The measured peak strain and acceleration response of the fundamental out of plane bending mode was significantly attenuated by adding a PID device. Attenuation of this mode is most relevant to the fatigue life of a PWA because the local relative displacements between the board and the supported components, which ultimately cause fatigue failures of the electrical leads of the board-mounted components are dominated by this mode. Applying PID damping at the board-level of assembly provides mitigation with a very small mass impact, especially as compared to isolation at an avionics box or shelf level of assembly. When compared with other mitigation techniques at the PWA level (board thickness, stiffeners, constrained layer damping), a compact PID device has the additional advantage of not needing to be an integral part of the design. A PID can simply be bonded to heritage or commercial off the shelf (COTS) hardware to facilitate its use in environments beyond which it was originally qualified. Finite element analysis and test results show that the beneficial effect is not localized and that the attenuation is not due to the simple addition of mass. No significant, detrimental reduction in frequency was observed. Side-by-side life testing of damped and un-damped boards at two different thicknesses (0.070" and 0.090") has shown that the addition of a PID was much more significant to the fatigue life than increasing the thickness. High speed video, accelerometer, and strain measurements have been collected to correlate with analytical results.
Knight, Brent↗
Command and Data Handling Branch Internship
Modular Integrated Stackable Layers (MISL) is a computer system designed for simple, fast, and cost effective flexible reconfiguration in space environments such as the ISS and Orion projects for various uses. Existing applications include wireless and wired communications, data acquisition and instrumentation, and camera systems, and potential applications include bus protocol converters and subsystem control. MISL is based on Texas Instruments (TI)' MSP430 16-bit ultra-low-power microcontroller device. The purpose of my project was to integrate the MISL system with a liquid crystal display (LCD) touchscreen. The LCD, manufactured by Crystalfontz and part number CFAF320240F-035T-TS, is a 320 by 240 RGB resistive color screen including an optional carrier board. The vast majority of the project was done with Altium Designer, a tool for printed circuit board (PCB) schematic capture, 3D design, and FPGA (Field Programmable Gate Array) development. The new PCB was to allow the LCD to directly stack to the rest of MISL. Research was done with datasheets for the TI microcontroller and touchscreen display in order to meet desired hardware specifications. Documentation on prior MISL projects was also utilized. The initial step was to create a schematic for the LCD, power bus, and data bus connections between components. A layout was then designed with the required physical dimensions, routed traces and vias, power and ground planes, layer stacks, and other specified design rules such as plane clearance and hole size. Multiple consultation sessions were held with Hester Yim, the technical discipline lead for the Command and Data Handling Branch, and Christy Herring, the lead PCB layout designer in the Electronic Design and Manufacturing Branch in order to ensure proper configuration. At the moment, the PCB is awaiting revision by the latter-mentioned branch. Afterwards, the board will begin to undergo the manufacturing and testing process. Throughout the internship at Johnson Space Center, I gained several technical and professional skills. I gained proficiency in Altium Designer and experience using subversion clients, as well as knowledge in PSpice with OrCAD and battery design for spaceflight from on-site. I also gained networking, organization, and communication skills throughout meetings with coworkers and other interns. This internship at Johnson Space Center has impacted my future aspirations by further inspiring me to follow a career path into space rated engineering technology and human spaceflight applications. After graduation, I plan to attend graduate Modular Integrated Stackable Layers (MISL) is a computer system designed for simple, fast, and cost effective flexible reconfiguration in space environments such as the ISS and Orion projects for various uses. Existing applications include wireless and wired communications, data acquisition and instrumentation, and camera systems, and potential applications include bus protocol converters and subsystem control. MISL is based on Texas Instruments’ MSP430 16 bit ultra-low power microcontroller device. The purpose of my project was to integrate the MISL system with a liquid crystal display touchscreen. The LCD, manufactured by Crystalfontz and part number CFAF320240F-035T-TS, is a 320x240 RGB resistive color screen including an optional carrier board.The vast majority of the project was done with Altium Designer, a tool for printed circuit board (PCB) schematic capture, 3D design, and FPGA development. The new PCB was to allow the LCD to directly stack to the rest of MISL. Research was done with datasheets for the TI microcontroller and touchscreen display in order to meet desired hardware specifications. Documentation on prior MISL projects was also utilized. The initial step was to create a schematic for the LCD, power bus, and data bus connections between components. A layout was then designed with the required physical dimensions, routed traces and vias, power and ground planes, layer stacks, and other specified design rules such as plane clearance and hole size. Multiple consultation sessions were held with Hester Yim, the technical discipline lead for the Command and Data Handling Branch, and Christy Herring, the lead PCB layout designer in the Electronic Design and Manufacturing Branch in order to ensure proper configuration. At themoment, the PCB is awaiting revision by the latter-mentioned branch. Afterwards, the board will begin to undergo the manufacturing and testing process.Throughout the internship at Johnson Space Center, I gained several technical and professional skills. I gained proficiency in Altium Designer and experience using subversion clients, as well as knowledge in PSpice with OrCAD and battery design for spaceflight from on-site. I also gained networking, organization, and communication skills throughout meetings with coworkers and other interns. This internship at Johnson Space Center has impacted my future aspirations by further inspiring me to follow a career path into space rated engineering technology and human spaceflight applications. After graduation, I plan to attend graduate school for a master's or doctorate degree in electrical or computer engineering.
Billings, Rachel Mae↗
Printed Circuit Board Design (PCB) with HDL Designer
Contents include the following: PCB design with HDL designer, design process and schematic capture - symbols and diagrams: 1. Motivation: time savings, money savings, simplicity. 2. Approach: use single tool PCB for FPGA design, more FPGA designs than PCB designers. 3. Use HDL designer for schematic capture.
Winkert, Thomas K.↗
Passive PCB Mounted Thermal Switch
A printed circuit board (PCB) generates heat during operation. In a vacuum this heat can only be rejected by conduction and radiation. In order to reject heat effectively the PCB needs to be thermally conductive to the electronics enclosure. However, when the enclosure temperature gets too low, too much heat is rejected from the PCB and it can fail. This thermal switch has been designed to allow for heat rejection when the PCB is sufficiently warm but then greatly reduce heat rejection when the temperature gets low enough.
Jarret Bone↗
Passive PCB Mounted Thermal Switch
A printed circuit board (PCB) generates heat during operation. In a vacuum this heat can only be rejected by conduction and radiation. To reject heat effectively and avoid overheating, the PCB needs to be thermally conductive to the electronics enclosure. However, if the system rejects too much heat, or not enough heat, either can result in system failure. The thermal switch will be able to regulate the amount of heat the system rejects to stay within the operational temperature range.
Jarret Bone↗
Design of Rigid-Flex PCB Robotics Leveraging Validated Finite Element Simulations
The use of rigid-flex printed circuit board (PCB) as primary structure has the potential to reduce the weight and volume of robotic systems. In the case of robotics for interplanetary exploration, these systems can leverage origami-inspired folding for increased mobility options and reduced storage volume. Folding rigid-flex PCB robotics can be constructed with rigid PCB connected by short Nomex fabric hinges coupled with flex PCB ribbon cables that permits enhanced system flexibility and energy dissipation to promote impact survivability. This paper presents a design methodology of rigid-flex PCB systems with an emphasis on impact resistance. The design process considers solder joint adequacy, panel bending, and fracture using a finite element (FE) model. The proposed design methodology is developed using a case study with NASA JPL's Pop-Up Folding Flat Explorer Robot (PUFFER). First, the finite-element (FE) modeling methodology is presented with consideration to both frequency and time-domain modeling applications, which include operational self-contact analysis and high impact scenarios. The time-domain impact modeling methodology utilizes hyperelastic material properties for the Nomex hinges. This modeling method is validated using image correlation of PUFFER drop tests. A flowchart is presented to guide users through a validated Abaqus modeling procedure for highly flexible rigid-flex systems. Next, a case study is presented in which PUFFER is subject to drop heights representative of falls into Lunar pits and then the design is refined for a more optimum impact performance. Finally, the results of the case study are used to inform a generalized design methodology for rigid-flex PCB robotics subject to high-impact loads with the considerations presented.
John Bell↗
Design of Rigid-Flex PCB Robotics Leveraging Validated Finite Element Simulations
The use of rigid-flex printed circuit board (PCB) as primary structure has the potential to reduce the weight and volume of robotic systems. In the case of robotics for interplanetary exploration, these systems can leverage origamiinspired folding for increased mobility options and reduced storage volume. Folding rigid-flex PCB robotics can be constructed with rigid PCB connected by short Nomex fabric hinges coupled with flex PCB ribbon cables that permits enhanced system flexibility and energy dissipation to promote impact survivability. This paper presents a design methodology of rigidflex PCB systems with an emphasis on impact resistance. The design process considers solder joint adequacy, panel bending, and fracture using a finite element (FE) model. The proposed design methodology is developed using a case study with NASA JPL’s Pop-Up Folding Flat Explorer Robot (PUFFER). First, the finite-element (FE) modeling methodology is presented with consideration to both frequency and time-domain modeling applications, which include operational self-contact analysis and high impact scenarios. The time-domain impact modeling methodology utilizes hyperelastic material properties for the Nomex hinges. This modeling method is validated using image correlation of PUFFER drop tests. A flowchart is presented to guide users through a validated Abaqus modeling procedure for highly flexible rigid-flex systems. Next, a case study is presented in which PUFFER is subject to drop heights representative of falls into Lunar pits and then the design is refined for a more optimum impact performance. Finally, the results of the case study are used to inform a generalized design methodology for rigid-flex PCB robotics subject to high-impact loads with the considerations presented.
de la Croix, Jean-Pierre↗
Compact Radar Transceiver with Included Calibration
The Digital Beamforming Synthetic Aperture Radar (DBSAR) is an eight-channel phased array radar system that employs solid-state radar transceivers, a microstrip patch antenna, and a reconfigurable waveform generator and processor unit. The original DBSAR transceiver design utilizes connectorized electronic components that tend to be physically large and heavy. To achieve increased functionality in a smaller volume, PCB (printed circuit board) transceivers were designed to replace the large connectorized transceivers. One of the most challenging problems designing the transceivers in a PCB format was achieving proper performance in the calibration path. For a radar loop-back calibration path, a portion of the transmit signal is coupled out of the antenna feed and fed back into the receiver. This is achieved using passive components for stability and repeatability. Some signal also leaks through the receive path. As these two signal paths are correlated via an unpredictable phase, the leakage through the receive path during transmit must be 30 dB below the calibration path. For DBSAR s design, this requirement called for a 100-dB isolation in the receiver path during transmit. A total of 16 solid-state L-band transceivers on a PCB format were designed. The transceivers include frequency conversion stages, T/R switching, and a calibration path capable of measuring the transmit power-receiver gain product during transmit for pulse-by-pulse calibration or matched filtering. In particular, this calibration path achieves 100-dB isolation between the transmitted signal and the low-noise amplifier through the use of a switching network and a section of physical walls achieving attenuation of radiated leakage. The transceivers were designed in microstrip PCBs with lumped elements and individually packaged components for compactness. Each transceiver was designed on a single PCB with a custom enclosure providing interior walls and compartments to isolate transceiver subsystems from radiated interference. The enclosure also acts as a heat sink for the voltage regulators and power amplifiers inside the system. The PCB transceiver design produces transmit pulses of 2 W with an arbitrary duty cycle. Each transceiver is fed by an external 120-MHz signal transmit and two 1,140-MHz local oscillator signals. The received signal is amplified and down-converted to 120 MHz and is fed to the data processor. The transceiver dimensions are approximately 3.5 11.5 0.6 in. (9 29 1.5 cm). The PCB transceiver design reduces the volume and weight of the DBSAR instrument while maintaining the functionality found in the original design. Both volume and weight are critical for airborne and flight remote sensing instrumentation.
McLinden, Matthew↗
Characterization of Low-Temperature, Co-Fired Ceramic-Manufactured Electrostatic Thruster-Closeout Report
The goal of the project was to evaluate prototypes of an experimental thruster developed by the University of Arkansas (UA), Fayetteville, AR. The design under evaluation is a radio frequency (RF) electrostatic thruster that was fabricated using the low-temperature, co-fired ceramic (LTCC) materials and fabrication process. This materials system is analogous to printed circuit board (PCB) technology with the most significant difference being that the laminate is replaced by a ceramic material and the copper layer is replaced by printed sinterable silver paste. LTCC designs are baked after fabrication and assembled to realize an entirely monolithic structure with internal conductors, vias, and cavities. In this process, the LTCC electrostatic thruster (LTCC-ET) that is the subject of the present work becomes a monolithic ceramic thruster capable of withstanding temperatures in excess of 500 ºC. The UA and NASA Marshall Space Flight Center (MSFC) jointly performed prototype testing on the LTCC-ET under a NASA Cooperative Agreement Notice (CAN) award. The LTCC-ET was tested at MSFC in May 2018 over a 1-week period. There were two goals for the test program: (1) Testing to determine the operating parameters required to create plasma ignition in the test articles. This was explored by setting a propellant flowrate and increasing RF power until plasma ignition was observed. Testing was conducted with both argon and krypton. (2) Investigate the thrust and specific impulse (Isp) performance of the thruster as a function of propellant flowrate and grid voltage. This goal was not met during the project as technical challenges in maintaining stable plasma ignition arose due to stress and heating of the RF power feed. In summary, a prototype thruster design (consisting of three packaged units) was fabricated by UA and tested for the first time under vacuum conditions at MSFC to experimentally determine basic performance metrics and functionality. It was found that the design was not sufficiently optimized or robust enough in its initial iteration to support a significant test campaign or characterization program. It was concluded that the propellant outlet channels must be reduced in size with the flowpaths adjusted to increase propellant residence time in the thruster, and that the RF connector must be replaced with a version capable of handling higher power throughput and heating. However, even in its unoptimized form, a plasma could be produced in the LTCCET, demonstrating the efficacy of the design approach. The design is especially compelling due to its low cost to manufacture and, more importantly, its scalability of size and power throughput. Low cost and scalability are also important in that additional functionalities, such as thrust vectoring and plume charge neutralization, can be integrated into future designs with minimal additional cost. This project has matured the LTCC-ET development Technology Readiness Level (TRL) from 1 to 2. The low-cost RF plasma source portion of the LTCC device was matured from TRL 2 to 4 through the demonstration of RF plasma ignition under vacuum conditions.
Huang, P.-H. A.↗
Modular Pulsed Plasma Electric Propulsion System for Cubesats
Current capabilities of CubeSats must be improved in order to perform more ambitious missions. Electric propulsion systems will play a key role due to their large specific impulse. Compared to other propulsion alternatives, their simplicity allows an easier miniaturization and manufacturing of autonomous modules into the nano and pico-satellite platform. Pulsed Plasma Thrusters (PPTs) appear as one of the most promising technologies for the near term. The utilization of solid and non-volatile propellants, their low power requirements and their proven reliability in the large scale make them great candidates for rapid implementation. The main challenges are the integration and miniaturization of all the electronic circuitry into a printed circuit board (PCB) that can satisfy the strict requirements that CubeSats present. NASA Ames and the George Washington University have demonstrated functionality and control of three discrete Micro-Cathode Arc Thrusters (CAT) using a bench top configuration that was compatible with the ARC PhoneSat Bus. This demonstration was successfully conducted in a vaccum chamber at the ARC Environmental Test Laboratory. A new effort will integrate a low power Plasma Processing Unit and two plasma thrusters onto a single printed circuit board that will utilize less than 13 U of Bus volume. The target design will be optimized for the accommodation into the PhoneSatEDISON Demonstration of SmallSatellite Networks (EDSN) bus as it uses the same software interface application, which was demonstrated in the previous task. This paper describes the design, integration and architecture of the proposed propulsion subsystem for a planned Technology Demonstration Mission. In addition, a general review of the Pulsed Plasma technology available for CubeSats is presented in order to assess the necessary challenges to overcome further development.
PCB↗
Impedance Discontinuity Reduction Between High-Speed Differential Connectors and PCB Interfaces
High-speed serial communication (i.e., Gigabit Ethernet) requires differential transmission and controlled impedances. Impedance control is essential throughout cabling, connector, and circuit board construction. An impedance discontinuity arises at the interface of a high-speed quadrax and twinax connectors and the attached printed circuit board (PCB). This discontinuity usually is lower impedance since the relative dielectric constant of the board is higher (i.e., polyimide approx. = 4) than the connector (Teflon approx. = 2.25). The discontinuity can be observed in transmit or receive eye diagrams, and can reduce the effective link margin of serial data networks. High-speed serial data network transmission improvements can be made at the connector-to-board interfaces as well as improving differential via hole impedances. The impedance discontinuity was improved by 10 percent by drilling a 20-mil (approx. = 0.5-mm) hole in between the pin of a differential connector spaced 55 mils (approx. = 1.4 mm) apart as it is attached to the PCB. The effective dielectric constant of the board can be lowered by drilling holes into the board material between the differential lines in a quadrax or twinax connector attachment points. The differential impedance is inversely proportional to the square root of the relative dielectric constant. This increases the differential impedance and thus reduces the above described impedance discontinuity. The differential via hole impedance can also be increased in the same manner. This technique can be extended to multiple smaller drilled holes as well as tapered holes (i.e., big in the middle followed by smaller ones diagonally).
Navidi, Sal↗
Reliability of CGA/LGA/HDI Package Board/Assembly (Final Report)
Package manufacturers are now offering commercial-off-the-shelf column grid array (COTS CGA) packaging technologies in high-reliability versions. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronics packages. The previous reports, released in January of 2012 and January of 2013, presented package test data, assembly information, and reliability evaluation by thermal cycling for CGA packages with 1752, 1517, 1509, and 1272 inputs/outputs (I/Os) and 1-mm pitch. It presented the thermal cycling (-55C either 100C or 125C) test results for up to 200 cycles. This report presents up to 500 thermal cycles with quality assurance and failure analysis evaluation represented by optical photomicrographs, 2D real time X-ray images, dye-and-pry photomicrographs, and optical/scanning electron Microscopy (SEM) cross-sectional images. The report also presents assembly challenge using reflowing by either vapor phase or rework station of CGA and land grid array (LGA) versions of three high I/O packages both ceramic and plastic configuration. A new test vehicle was designed having high density interconnect (HDI) printed circuit board (PCB) with microvia-in-pad to accommodate both LGA packages as well as a large number of fine pitch ball grid arrays (BGAs). The LGAs either were assembled onto HDI PCB as an LGA or were solder paste print and reflow first to form solder dome on pads before assembly. Both plastic BGAs with 1156 I/O and ceramic LGAs were assembled. It also presented the X-ray inspection results as well as failures due to 200 thermal cycles. Lessons learned on assembly of ceramic LGAs are also presented.
Ghaffaroam. Reza↗
Embedded passives emulator FY2003 interim report
The National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program has been evaluating state-of-the-art Embedded Passive Technology for the printed circuit board (PCB) industry for the past several years and has conducted its own testing on embedded passive coupons (resistors and capacitors). This document is a progress report of the work performed through fiscal year 2008 by NASA and the Navy to convert an existing PWB (printed wiring board) design to a design that incorporates embedded passive components. The work is being performed through a memorandum of understanding (MOU) between the NEPP Program (NASA) and the Naval Surface Warfare Center (NSWC) Crane Emerging Critical Interconnect Technology (ECIT) Program. NSWC Crane’s ECIT Program has funding to convert two PCB designs from the military and aerospace industry to a PCB design with embedded passives. ECIT will provide a design team that will take a well characterized design and convert it to an embedded design. They will also provide electrical modeling and layout expertise as well as build the PWB in their facility in Indiana. NEPP, through the Jet Propulsion Laboratory (JPL), will assemble any passives deemed not suitable for embedding and the active components and electrically test the new design to the existing (non-embedded) design
Gerke, David↗
Distributed Capacitive Sensor for Sample Mass Measurement
Previous robotic sample return missions lacked in situ sample verification/ quantity measurement instruments. Therefore, the outcome of the mission remained unclear until spacecraft return. In situ sample verification systems such as this Distributed Capacitive (DisC) sensor would enable an unmanned spacecraft system to re-attempt the sample acquisition procedures until the capture of desired sample quantity is positively confirmed, thereby maximizing the prospect for scientific reward. The DisC device contains a 10-cm-diameter pressure-sensitive elastic membrane placed at the bottom of a sample canister. The membrane deforms under the weight of accumulating planetary sample. The membrane is positioned in close proximity to an opposing rigid substrate with a narrow gap. The deformation of the membrane makes the gap narrower, resulting in increased capacitance between the two parallel plates (elastic membrane and rigid substrate). C-V conversion circuits on a nearby PCB (printed circuit board) provide capacitance readout via LVDS (low-voltage differential signaling) interface. The capacitance method was chosen over other potential approaches such as the piezoelectric method because of its inherent temperature stability advantage. A reference capacitor and temperature sensor are embedded in the system to compensate for temperature effects. The pressure-sensitive membranes are aluminum 6061, stainless steel (SUS) 403, and metal-coated polyimide plates. The thicknesses of these membranes range from 250 to 500 m. The rigid substrate is made with a 1- to 2-mm-thick wafer of one of the following materials depending on the application requirements glass, silicon, polyimide, PCB substrate. The glass substrate is fabricated by a microelectromechanical systems (MEMS) fabrication approach. Several concentric electrode patterns are printed on the substrate. The initial gap between the two plates, 100 m, is defined by a silicon spacer ring that is anodically bonded to the glass substrate. The fabricated proof-of-concept devices have successfully demonstrated tens to hundreds of picofarads of capacitance change when a simulated sample (100 g to 500 g) is placed on the membrane.
Toda, Risaku↗
Laboratory Radar Measurements in Support of the NASA Orbital Debris Program Office’s Size Estimation Model
The NASA Orbital Debris Program Office (ODPO) relies on ground-based radar measurements from both the Haystack Ultrawideband Satellite Imaging Radar (HUSIR) and the Goldstone Solar System Radar (Goldstone) to characterize mm to cm debris population in low Earth orbit (LEO). Radar measurements help characterize the size of orbital debris objects, particularly fragmentation debris. However, debris size is not directly measured by radar but inferred from the measured radar cross section (RCS) which depends on several parameters in addition to physical size including electrical conductivity and polarization. To interpret the observed RCS of orbital debris objects detected by radar measurements as physical sizes, NASA uses an empirical size estimation model (SEM) based on laboratory RCS measurements of breakup fragments generated during hypervelocity impact tests as well as some pieces of non-impact-generated “artificial” debris-like objects expected to be representative of the debris population. Since the development of the ODPO SEM, many new materials have been introduced to spacecraft construction. Consequently, ODPO plans to update the radar SEM based on planned laboratory RCS measurements of debris fragments from DebriSat, a ground-based hypervelocity impact experiment conducted in 2014 that consisted of a high-fidelity spacecraft model characteristic of a modern LEO spacecraft. Prior to measuring DebriSat fragments, a set of calibration targets with well-defined geometries and material compositions were measured at The Ohio State University’s ElectroScience Laboratory (OSU-ESL) compact radar range. These calibration measurements help to validate, and understand any limitations of, laboratory measurements of RCS. Calibration targets include idealizations of typical shape categories seen in DebriSat fragments such as nuggets, flat plates, and cylinders. As with DebriSat, calibration target materials were chosen to represent typical modern-day spacecraft components and include stainless steel, aluminum, printed circuit board (PCB) substrate, and carbon fiber-reinforced polymer (CFRP). These materials also represent a wide range of electrical conductivities, which strongly influences measured RCS and inferred target size. The RCS calibration measurements were collected over a frequency sweep from 2 to 18 GHz and stepping through different azimuth angles from 0 to 360 degrees at an elevation of 0 degrees. A second set of calibration measurements is in work consisting of more complex shapes such as bent rods and plates as well as different mounting options including epoxy and a 3D printed holder. These further measurements along with our initial calibration set will inform selection of representative DebriSat fragments for laboratory RCS measurements that will contribute to the planned update to the ODPO radar SEM. An appropriate subset of both the radar calibration and DebriSat samples will also be measured in the ODPO Optical Measurements Center to cross-calibrate size estimates over these different wavelength regimes.
Radar↗
Ultra-Wideband Array in PCB for Millimeter-Wave 5G and ISM
Growing mobile data consumption has prompted the exploration of the millimeter-wave spectrum for large bandwidth, high speed communications. However, the allocated bands are spread across a wide swath of spectrum: Fifth generation mobile architecture (5G): 28, 38, 39, 6471 GHz; Industrial, Scientific, and Medical bands (ISM): 24, 60 GHz. Moreover, high gain phased arrays are required to overcome the significant path loss associated with these frequencies. Further, it is necessary to incorporate several of these applications in a single, small size and low cost platform. To this end, we have developed a scanning, Ultra-Wideband (UWB) array which covers all 5G, ISM, and other mm-W bands from 2472 GHz. Critically, this is accomplished using mass-production Printed Circuit Board (PCB) fabrication. The results of this work are presented in this poster.
Milli-Meter Wave↗
Packaging printed circuit boards: A production application of interactive graphics
The structure and use of an Interactive Graphics Packaging Program (IGPP), conceived to apply computer graphics to the design of packaging electronic circuits onto printed circuit boards (PCB), were described. The intent was to combine the data storage and manipulative power of the computer with the imaginative, intuitive power of a human designer. The hardware includes a CDC 6400 computer and two CDC 777 terminals with CRT screens, light pens, and keyboards. The program is written in FORTRAN 4 extended with the exception of a few functions coded in COMPASS (assembly language). The IGPP performs four major functions for the designer: (1) data input and display, (2) component placement (automatic or manual), (3) conductor path routing (automatic or manual), and (4) data output. The most complex PCB packaged to date measured 16.5 cm by 19 cm and contained 380 components, two layers of ground planes and four layers of conductors mixed with ground planes.
Perrill, W. A.↗