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At least 19 records

Development of low cost, high reliability sealing techniques for hybrid microcircuit packages. Phase 2, supplement 1: Moisture permeation of adhesive-sealed hybrid microcircuit packages

The susceptibility of adhesive-sealed ceramic packages to moisture permeation was investigated. The two adhesives, Ablebond 789-1 and Epo-Tek H77, were evaluated as package sealants. These adhesives were previously selected as the most promising candidates for this application from a group of ten adhesives. Ceramic packages sealed with these adhesives were exposed to temperature-humidity conditions of 25 C/98 percent RH, 50 C/60 percent RH, 50 C/98 percent RH, and 85 C/85 percent RH and their moisture contents using were monitored solid state moisture sensors sealed inside them. Five packages were tested at each of these exposures - two ceramic packages sealed with each of the two adhesives and one seam-sealed gold-plated Kovar package. This latter package was included to serve as a control. The results showed that the adhesive-sealed packages were not hermetic to moisture. The rates at which moisture entered the packages increased with the severity of the exposure environments (i.e., higher temperatures and higher moisture vapor pressures) with greater dependence on temperature than on moisture vapor pressure.

Perkins, K. L.

Advanced Packaging Materials and Techniques for High Power TR Module: Standard Flight vs. Advanced Packaging

The higher output power densities required of modern radar architectures, such as the proposed DESDynI [Deformation, Ecosystem Structure, and Dynamics of Ice] SAR [Synthetic Aperture Radar] Instrument (or DSI) require increasingly dense high power electronics. To enable these higher power densities, while maintaining or even improving hardware reliability, requires advances in integrating advanced thermal packaging technologies into radar transmit/receive (TR) modules. New materials and techniques have been studied and compared to standard technologies.

Deformation, Ecosystem Structure, and Dynamics of

Analysis of ITT scan bearing package (bearing package S/N 7-1004)

A geostationary operational environments satellite (GOES) East-West scan-bearing assembly was examined after having completed two and one-half years of operation. The following results were found: (1) lubrication breakdown was found in both bearings; (2) patchy wear-bands running only approximately half-way around the races indicated a load distribution in the ball groups consistent with a very low preload; (3) contact angles of 31.2 deg (S/N 1004) and 28.7 deg (S/N 1004A) were found in bearings whose contact angles are supposed to be 20+/-2 deg; and (4) contamination was present in the bearings.

Gelotte, Erik

3D printing of packaging inserts from biomass-fungi composites: Environmental sustainability analysis

In this study, a comprehensive Life cycle assessment (LCA) is conducted on molded packaging inserts from expanded polystyrene (EPS) foam, molded packaging inserts from biomass-fungi composite, and 3D-printed packaging inserts from biomass-fungi composite under the low mix / high volume (LMHV) scenario and molded and machined packaging inserts from EPS foam, molded and machined packaging inserts from biomass-fungi composite, and 3D-printed packaging inserts from biomass-fungi composite under the high mix / low volume (HMLV) scenario. Six environmental impact categories—climate change, acidification, eutrophication, fossil resource scarcity, land use, and water consumption—are analyzed to evaluate the environmental trade-offs associated with each type of packaging inserts. Under the LMHV scenario, molded packaging inserts from biomass-fungi composite emerge as the best option due to their lower impact on climate change, acidification and water consumption compared to other types of packaging inserts. Conversely, molded packaging inserts from biomass-fungi composite face challenges in land use and eutrophication, primarily due to raw material production. LCA also reveals that 3D-printed packaging inserts from biomass-fungi composite are the most environmentally favorable option under the HMLV scenario, due to significantly lower contributions to climate change, eutrophication, and water consumption compared to other types of packaging inserts. Conversely, 3D-printed packaging inserts from biomass-fungi composite face challenges in acidification and land use, primarily due to raw material production. As part of the LCA, sensitivity analyses show that sourcing energy from 100% renewable sources substantially lowers climate change impacts across all packaging types, while varying transportation distances results in only minor changes, indicating the dominant role of upstream material and manufacturing processes. Additional sensitivity analysis is conducted under the HMLV scenario to assess the impact of material removal during machining on the environment. The amount of material removal is varied from 10 to 70% for the sensitivity analysis and it highlights that the amount of material removed during machining has no significant impact on climate change for packaging inserts from EPS foam. However, molded and machined packaging inserts from biomass-fungi composite show an increasing trend in climate change with higher amount of material removal, while 3D-printed packaging inserts from biomass-fungi composite exhibit a decreasing trend, driven by reduced raw material usage and energy consumption.

09 BIOMASS FUELS

Reliability of High I/O High Density CCGA Interconnect Electronic Packages under Extreme Thermal Environment

This paper provides the experimental test results of advanced CCGA packages tested in extreme temperature thermal environments. Standard optical inspection and x-ray non-destructive inspection tools were used to assess the reliability of high density CCGA packages for deep space extreme temperature missions. Ceramic column grid array (CCGA) packages have been increasing in use based on their advantages such as high interconnect density, very good thermal and electrical performances, compatibility with standard surface-mount packaging assembly processes, and so on. CCGA packages are used in space applications such as in logic and microprocessor functions, telecommunications, payload electronics, and flight avionics. As these packages tend to have less solder joint strain relief than leaded packages or more strain relief over lead-less chip carrier packages, the reliability of CCGA packages is very important for short-term and long-term deep space missions. We have employed high density CCGA 1152 and 1272 daisy chained electronic packages in this preliminary reliability study. Each package is divided into several daisy-chained sections. The physical dimensions of CCGA1152 package is 35 mm x 35 mm with a 34 x 34 array of columns with a 1 mm pitch. The dimension of the CCGA1272 package is 37.5 mm x 37.5 mm with a 36 x 36 array with a 1 mm pitch. The columns are made up of 80% Pb/20%Sn material. CCGA interconnect electronic package printed wiring polyimide boards have been assembled and inspected using non-destructive x-ray imaging techniques. The assembled CCGA boards were subjected to extreme temperature thermal atmospheric cycling to assess their reliability for future deep space missions. The resistance of daisy-chained interconnect sections were monitored continuously during thermal cycling. This paper provides the experimental test results of advanced CCGA packages tested in extreme temperature thermal environments. Standard optical inspection and x-ray non-destructive inspection tools were used to assess the reliability of high density CCGA packages for deep space extreme temperature missions. Keywords: Extreme temperatures, High density CCGA qualification, CCGA reliability, solder joint failures, optical inspection, and x-ray inspection.

high density CCGA qualifications

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Electronic packaging

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Chen, Liang-Yu

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

dielectric properties

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature