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Probing the Effects of the First Atomic Layer on the Dynamic Behavior of Sub-2 nm MgO/Al 2 O 3 Memristors

As electronic devices continue to scale down from the current sub-5 nm range, atomic-scale control of defects becomes increasingly crucial to suppressing their impact on the physical properties of the devices. Memristors present an excellent example as a nonlinear and dynamic device with high speed and endurance required for electronic applications ranging from neuromorphic computing to nonvolatile memories. Herein we investigate the impact of atomic defects in sub-2 nm thick MgO/Al 2 O 3 atomic layer stack (ALS) memristors that use an M1 (switching layer)/M2 (oxygen vacancy reservoir layer) bilayer structure grown using in vacuo atomic layer deposition (iALD). Intriguingly, we revealed a direct correlation of the atomic defects in the M2 layer with the memristor dynamic behavior using a combined analysis of in situ scanning tunneling spectroscopy (iSTS) on the M2 layer and ex situ characterization on the memristors. Specifically, incomplete coverage of the 1st ALD atomic layer of M2 on the electrode yields defects at the M2/electrode interface. Despite the monotonic increase of ALD coverage, by almost three-fold from ~30% to >90%, at completion of the M2 layer of ~ 0.7 nm in thickness, the impact of the defects on the M2/electrode interface has been found detrimental to both memristor switching speed and endurance. Guided by atomistic simulation, we addressed the issue of interface defects via tuning of the Al surface hydroxylation to increase the first atomic layer ALD coverage to ~75%, leading to improved memristor switching speed and endurance by several orders of magnitude. In conclusion, these findings shed light on the correlation between the atomic defects and the dynamic behavior of sub-2 nm memristors and the importance of minimizing the atomic defects in memristors for future electronic applications.

Atomic Layer Deposition

ALD-Derived WO 3– x Leads to Nearly Wake-Up-Free Ferroelectric Hf 0.5 Zr 0.5 O 2 at Elevated Temperatures

Breaking the memory wall in advanced computing architectures will require complex 3D integration of emerging memory materials such as ferroelectrics─either within the back-end-of-line (BEOL) of CMOS front-end processes or through advanced 3D packaging technologies. Achieving this integration demands that memory materials exhibit high thermal resilience, with the capability to operate reliably at elevated temperatures, such as 125°C, due to the substantial heat generated by front-end transistors. However, silicon-compatible HfO 2 -based ferroelectrics tend to exhibit antiferroelectric-like behavior in this temperature range, accompanied by a more pronounced wake-up effect, posing significant challenges to their thermal reliability. Here, we report that by introducing a thin tungsten oxide (WO 3–x ) layer─known as an oxygen reservoir─and carefully tuning its oxygen content, ultrathin Hf 0.5 Zr 0.5 O 2 (5 nm) films can be made robust against the ferroelectric-to-antiferroelectric transition at elevated temperatures. This approach not only minimizes polarization loss in the pristine state but also effectively suppresses the wake-up effect, reducing the required wake-up cycles from 10 5 to only 10 at 125°C, a qualifying temperature for back-end memory integrated with front-end logic, as defined by the JEDEC standard. First-principles density functional theory (DFT) calculations reveal that WO 3 enhances the stability of the ferroelectric orthorhombic phase (o-phase) at elevated temperatures by increasing the tetragonal-to-orthorhombic phase energy gap and promoting favorable phonon mode evolution, thereby supporting o-phase formation under both thermodynamic and kinetic constraints.

36 MATERIALS SCIENCE