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Toughening of interface networks through the introduction of weak links
The resistance of polycrystalline materials to intergranular fracture depends on the toughness of the interfaces between neighboring grains. Using finite element simulations on model, two-dimensional microstructures, we demonstrate that the steady-state crack growth resistance of a polycrystal that contains exclusively high toughness interfaces is suboptimal: its crack growth resistance may be increased by introducing a minority fraction of weak interfaces at random locations within the interface network. Furthermore, the weaker are these interfaces, the greater is their toughening effect. These weak interfaces toughen the material through crack deflection and branching, nucleation of secondary cracks, and inelastic dissipation within intact interfaces. Furthermore, our findings suggest that fracture resistance-oriented material development should not aim to eliminate all weak interfaces, but rather judiciously incorporate a low fraction of them.
In-network compute assistance
A method and apparatus for performing operations by network interface cards in a network of computers. A network interface card is configured to receive a message and to interpret the message to identify a primitive operation to be performed. The primitive operation is one of a plurality of primitive operations that are performed to perform an operation. The primitive operation is performed by the network interface card and a trigger signal is generated in response to performing the primitive operation. The trigger signal is interpreted to identify a triggered message. The triggered message identifies a next one of the plurality of primitive operations to be performed. The triggered message is transmitted back to the network interface card or to another network interface card in the network for processing.
The Portals 4.3 Network Programming Interface
This report presents a specification for the Portals 4 network programming interface. Portals 4 is intended to allow scalable, high-performance network communication between nodes of a parallel computing system. Portals 4 is well suited to massively parallel processing and embedded systems. Portals 4 represents an adaption of the data movement layer developed for massively parallel processing platforms, such as the 4500-node Intel TeraFLOPS machine. Sandia's Cplant cluster project motivated the development of Version 3.0, which was later extended to Version 3.3 as part of the Cray Red Storm machine and XT line. Version 4 is targeted to the next generation of machines employing advanced network interface architectures that support enhanced offload capabilities.
Networks and interfaces as catalysts for polymer materials innovation
Autonomous experimental systems offer a compelling glimpse into a future where closed-loop, iterative cycles—performed by machines and guided by artificial intelligence (AI) and machine learning (ML)—play a foundational role in materials research and development. This perspective draws attention to the roles of networks and interfaces—of and between humans and machines—for the purpose of generating knowledge and accelerating innovation. Polymers, a class of materials with massive global impact, present a unique opportunity for the application of informatics and automation to pressing societal challenges. To develop these networks and interfaces in polymer science, the Community Resource for Innovation in Polymer Technology (CRIPT)—a polymer data ecosystem based on novel polymer data model, representation, search, and visualization technologies—is introduced. The ongoing co-design efforts engage stakeholders in industry, academia, and government to uncover rapidly actionable, high-impact opportunities to build networks, bridge interfaces, and catalyze innovation in polymer technology.
Caffeine: CoArray Fortran Framework of Efficient Interfaces to Network Environments
This paper provides an introduction to the CoArray Fortran Framework of Efficient Interfaces to Network Environments (Caffeine), a parallel runtime library built atop the GASNet-EX exascale networking library. Caffeine leverages several non-parallel Fortran features to write type- and rank-agnostic interfaces and corresponding procedure definitions that support parallel Fortran 2018 features, including communication, collective operations, and related services. One major goal is to develop a runtime library that can eventually be considered for adoption by LLVM Flang, enabling that compiler to support the parallel features of Fortran. The paper describes the motivations behind Caffeine's design and implementation decisions, details the current state of Caffeine's development, and previews future work. We explain how the design and implementation offer benefits related to software sustainability by lowering the barrier to user contributions, reducing complexity through the use of Fortran 2018 C-interoperability features, and high performance through the use of a lightweight communication substrate.
Quantum oscillations from networked topological interfaces in a Weyl semimetal
Layered transition metal chalcogenides are promising hosts of electronic Weyl nodes and topological superconductivity. MoTe 2 is a striking example that harbors both noncentrosymmetric T d and centrosymmetric T’ phases, both of which have been identified as topologically nontrivial. Applied pressure tunes the structural transition separating these phases to zero temperature, stabilizing a mixed T d –T’ matrix that entails a network of interfaces between the two nontrivial topological phases. Here, we show that this critical pressure range is characterized by distinct coherent quantum oscillations, indicating that the difference in topology between topologically nonvtrivial T d and T’ phases gives rise to an emergent electronic structure: a network of topological interfaces. A rare combination of topologically nontrivial electronic structures and locked-in transformation barriers leads to this counterintuitive situation, wherein quantum oscillations can be observed in a structurally inhomogeneous material. These results further open the possibility of stabilizing multiple topological phases coexisting with superconductivity.
“Smarter” NICs for faster algorithms [Slides]
The basic building block of a distributed-memory cluster or supercomputer is a node. Each node includes a host, which is a processor (xPU) + memory hierarchy. The host can communicate with other hosts via its NIC (network interface controller). A network connects the nodes. The nodes may be arranged in some topology, which determines the network’s carrying capacity and cost.
Considerations and recent advances in nanoscale interfaces with neuronal and cardiac networks
Nanoscale interfaces with biological tissue, principally made with nanowires (NWs), are envisioned as minimally destructive to the tissue and as scalable tools to directly transduce the electrochemical activity of a neuron at its finest resolution. This review lays the foundations for understanding the material and device considerations required to interrogate neuronal activity at the nanoscale. We first discuss the electrochemical nanoelectrode-neuron interfaces and then present new results concerning the electrochemical impedance and charge injection capacities of millimeter, micrometer, and nanometer scale wires with Pt, PEDOT:PSS, Si, Ti, ITO, IrO x , Ag, and AgCl materials. Using established circuit models for NW-neuron interfaces, we discuss the impact of having multiple NWs interfacing with a single neuron on the amplitude and temporal characteristics of the recorded potentials. We review state of the art advances in nanoelectrode-neuron interfaces, the standard control experiments to investigate their electrophysiological behavior, and present recent high fidelity recordings of intracellular potentials obtained with ultrasharp NWs developed in our laboratory that naturally permeate neuronal cell bodies. Recordings from arrays and individually addressable electrically shorted NWs are presented, and the long-term stability of intracellular recording is discussed and put in the context of established techniques. Finally, a perspective on future research directions and applications is presented.
Interface PINNs (I-PINNs): A physics-informed neural networks framework for interface problems
Here, we present a novel physics-informed neural networks (PINNs) framework for modeling interface problems, termed Interface PINNs (I-PINNs). I-PINNs uses different neural networks for any two subdomains separated by a sharp interface such that the neural networks differ only through their activation functions while the other parameters remain identical. The performance of I-PINNs, conventional PINNs, and other existing domain-decomposition PINNs methods such as extended PINNs (XPINNs) and multi-domain PINN (M-PINN) is compared through several one-dimensional, two-dimensional, and three-dimensional benchmark elliptic interface problems. The results demonstrate that I-PINNs provides a root-mean-square-error accuracy, at least two orders of magnitude better than conventional PINNs and XPINNs at approximately one-tenth of the computational cost of conventional PINNs and half the cost of XPINNs. Additionally, while I-PINNs and M-PINN provide comparable accuracies, M-PINN is found to be approximately 50% more expensive.
Network packet templating for GPU-initiated communication
Systems, apparatuses, and methods for performing network packet templating for graphics processing unit (GPU)-initiated communication are disclosed. A central processing unit (CPU) creates a network packet according to a template and populates a first subset of fields of the network packet with static data. Next, the CPU stores the network packet in a memory. A GPU initiates execution of a kernel and detects a network communication request within the kernel and prior to the kernel completing execution. Responsive to this determination, the GPU populates a second subset of fields of the network packet with runtime data. Then, the GPU generates a notification that the network packet is ready to be processed. A network interface controller (NIC) processes the network packet using data retrieved from the first subset of fields and from the second subset of fields responsive to detecting the notification.
Path-synchronous performance monitoring of interconnection networks based on source code attribution
Examples disclosed herein relate to path-synchronous performance monitoring of an interconnection network based on source code attribution. A processing node in the interconnection network has a profiler module to select a network transaction to be monitored, determine a source code attribution associated with the network transaction to be monitored, and issue a network command to execute the network transaction to be monitored. A logger module creates, in a buffer, a node temporal log associated with the network transaction and the network command. A drainer module periodically captures the node temporal log. The processing node has a network interface controller to receive the network command and mark a packet generated for the network command to be temporally tracked and attributed back to the source code attribution at each hop of the interconnection network traversed by the marked packet.
Adaptive Interface-PINNs (AdaI-PINNs): An Efficient Physics-Informed Neural Networks Framework for Interface Problems
Here, we present an efficient physics-informed neural networks (PINNs) framework, termed Adaptive Interface-PINNs (AdaI-PINNs), to improve the modeling of interface problems with discontinuous coefficients and/or interfacial jumps. This framework is an enhanced version of its predecessor, Interface PINNs or I-PINNs (Sarma et al.; https://doi.org/10.1016/j.cma.2024.117135), which involves domain decomposition and assignment of different predefined activation functions to the neural networks in each subdomain across a sharp interface, while keeping all other parameters of the neural networks identical. In AdaI-PINNs, the activation functions vary solely in their slopes, which are trained along with the other parameters of the neural networks. This makes the AdaI-PINNs framework fully automated without requiring preset activation functions. Comparative studies on one-dimensional, two-dimensional, and three-dimensional benchmark elliptic interface problems reveal that AdaI-PINNs outperform I-PINNs, reducing computational costs by 2-6 times while producing similar or better accuracy.
Network traffic control for multi-homed end-hosts via SDN
Software-defined networking (SDN) is an emerging technology of efficiently controlling and managing computer networks, such as in data centres, wide-area networks, as well as in ubiquitous communication. In this study, the authors explore the idea of embedding the SDN components, represented by SDN controller and virtual switch, in end-hosts to improve network performance. In particular, the authors consider load balancing across multiple network interfaces on end-hosts with different link capacity scenarios. The authors have explored and implemented different SDN-based load-balancing approaches based on OpenFlow software switches, and have demonstrated the feasibility and the potential of this approach. The proposed system has been evaluated with MultiPath transmission control protocol (MPTCP). Furthermore, the proposed results demonstrated the potential of applying the SDN concepts on multi-homed devices resulting in an increase in achieved throughput of 55% compared to the legacy single network approach and 10% compared to the MPTCP.
CommBench: Micro-Benchmarking Hierarchical Networks with Multi-GPU, Multi-NIC Nodes
Modern high-performance computing systems have multiple GPUs and network interface cards (NICs) per node. The resulting network architectures have multilevel hierarchies of subnetworks with different interconnect and software technologies. These systems offer multiple vendor-provided communication capabilities and library implementations (IPC, MPI, NCCL, RCCL, OneCCL) with APIs providing varying levels of performance across the different levels. Understanding this performance is currently difficult because of the wide range of architectures and programming models (CUDA, HIP, OneAPI). We present CommBench, a library with cross-system portability and a high-level API that enables developers to easily build microbenchmarks relevant to their use cases and gain insight into the performance (bandwidth & latency) of multiple implementation libraries on different networks. We demonstrate CommBench with three sets of microbenchmarks that profile the performance of six systems. Our experimental results reveal the effect of multiple NICs on optimizing the bandwidth across nodes and also present the performance characteristics of four available communication libraries within and across nodes of NVIDIA, AMD, and Intel GPU networks.
Optical networking within the Lightwave Energy-Efficient Datacenter project [Invited]
The Lightwave Energy-Efficient Datacenter (LEED) project within the ARPA-e ENLITENED program is developing novel energy-efficient multichannel lightwave networks. These networks are enabled by a new optical “rotor” switch that can reconfigure the network topology in less than 20 µs and a field-programmable-gate-array-based network interface controller called Corundum that can provide precise network-wide synchronization of packets admitted into the lightwave network. Here we review the optical networking research within LEED and discuss future directions.
Performance Characteristics of the BlueField-2 SmartNIC
High-performance computing (HPC) researchers have long envisioned scenarios where application workflows could be improved through the use of programmable processing elements embedded in the network fabric. Recently, vendors have introduced programmable Smart Network Interface Cards (SmartNICs) that enable computations to be offloaded to the edge of the network. There is great interest in both the HPC and high-performance data analytics (HPDA) communities in understanding the roles these devices may play in the data paths of upcoming systems. This paper focuses on characterizing both the networking and computing aspects of NVIDIA’s new BlueField-2 SmartNIC when used in a 100Gb/s Ethernet environment. For the networking evaluation we conducted multiple transfer experiments between processors located at the host, the SmartNIC, and a remote host. These tests illuminate how much effort is required to saturate the network and help estimate the processing headroom available on the SmartNIC during transfers. For the computing evaluation we used the stress-ng benchmark to compare the BlueField-2 to other servers and place realistic bounds on the types of offload operations that are appropriate for the hardware. Our findings from this work indicate that while the BlueField-2 provides a flexible means of processing data at the network’s edge, great care must be taken to not overwhelm the hardware. While the host can easily saturate the network link, the SmartNIC’s embedded processors may not have enough computing resources to sustain more than half the expected bandwidth when using kernel-space packet processing. From a computational perspective, encryption operations, memory operations under contention, and on-card IPC operations on the SmartNIC perform significantly better than the general-purpose servers used for comparisons in our experiments. Therefore, applications that mainly focus on these operations may be good candidates for offloading to the SmartNIC.
Processing Particle Data Flows with SmartNICs
Many distributed applications implement complex data flows and need a flexible mechanism for routing data between producers and consumers. Recent advances in programmable network interface cards, or SmartNICs, represent an opportunity to offload data-flow tasks into the network fabric, thereby freeing the hosts to perform other work. System architects in this space face multiple questions about the best way to leverage SmartNICs as processing elements in data flows. In this paper, we advocate the use of Apache Arrow as a foundation for implementing data-flow tasks on SmartNICs. We report on our experiences adapting a partitioning algorithm for particle data to Apache Arrow and measure the on-card processing performance for the BlueField-2 SmartNIC. Our experiments confirm that the BlueField-2’s (de)compression hardware can have a significant impact on in-transit workflows where data must be unpacked, processed, and repacked.