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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2011

Enabling Future Robotic Missions with Multicore Processors

Recent commercial developments in multicore processors (e.g. Tilera, Clearspeed, HyperX) have provided an option for high performance embedded computing that rivals the performance attainable with FPGA-based reconfigurable computing architectures. Furthermore, these processors offer more straightforward and streamlined application development by allowing the use of conventional programming languages and software tools in lieu of hardware design languages such as VHDL and Verilog. With these advantages, multicore processors can significantly enhance the capabilities of future robotic space missions. This paper will discuss these benefits, along with onboard processing applications where multicore processing can offer advantages over existing or competing approaches. This paper will also discuss the key artchitecural features of current commercial multicore processors. In comparison to the current art, the features and advancements necessary for spaceflight multicore processors will be identified. These include power reduction, radiation hardening, inherent fault tolerance, and support for common spacecraft bus interfaces. Lastly, this paper will explore how multicore processors might evolve with advances in electronics technology and how avionics architectures might evolve once multicore processors are inserted into NASA robotic spacecraft.

multi-core processor↗
DOE OSTI2021

$\mathrm{PPT}$-Multicore: performance prediction of Open$\mathrm{MP}$ applications using reuse profiles and analytical modeling

In this report we present PPT-Multicore, an analytical model embedded in the Performance Prediction Toolkit (PPT) to predict parallel applications’ performance running on a multicore processor. PPT-Multicore builds upon our previous work towards a multicore cache model. We extract LLVM basic block labeled memory trace using an architecture-independent LLVM-based instrumentation tool only once in an application’s lifetime. The model uses the memory trace and other parameters from an instrumented sequentially executed binary. We use probabilistic and computationally efficient reuse profiles to predict the cache hit rates and runtimes of OpenMP programs’ parallel sections. We model Intel’s Broadwell, Haswell, and AMD’s Zen2 architectures and validate our framework using different applications from PolyBench and PARSEC benchmark suites. The results show that PPT-Multicore can predict cache hit rates with an overall average error rate of 1.23% while predicting the runtime with an error rate of 9.08%.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2013

Multicore Considerations for Legacy Flight Software Migration

In this paper we will discuss potential benefits and pitfalls when considering a migration from an existing single core code base to a multicore processor implementation. The results of this study present options that should be considered before migrating fault managers, device handlers and tasks with time-constrained requirements to a multicore flight software environment. Possible future multicore test bed demonstrations are also discussed.

legacy flight software↗
DOE OSTI2019

Connectors for multicore optical fibers and methods thereof

The present invention relates to optical coupling systems that employ a multicore optical fiber. The system can be employed with two multicore optical fibers or with a single multicore optical fiber for use with an optical device. In particular, the system includes connectors having a lens assembly configured to relay optical signals and a ferrule to position the lens assembly. Additional details for making and using such systems are described herein.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
NASA NTRS2012

Real-Time Adaptive Lossless Hyperspectral Image Compression using CCSDS on Parallel GPGPU and Multicore Processor Systems

The proposed CCSDS (Consultative Committee for Space Data Systems) Lossless Hyperspectral Image Compression Algorithm was designed to facilitate a fast hardware implementation. This paper analyses that algorithm with regard to available parallelism and describes fast parallel implementations in software for GPGPU and Multicore CPU architectures. We show that careful software implementation, using hardware acceleration in the form of GPGPUs or even just multicore processors, can exceed the performance of existing hardware and software implementations by up to 11x and break the real-time barrier for the first time for a typical test application.

realtime↗
DOE OSTI2019

Optimal design of a single-mode trench-assisted homogeneous multicore fibre with a minimum crosstalk level

We have proposed an optimal design of five different core structures (St1 – St5) for a seven-core trench-assisted multicore fibre, whose core radius and relative core/cladding refractive index difference Δ{sub 1} are optimal for single-mode propagation. The crosstalk performance and its reduction (in dB) with respect to variations in fibre design parameters, such as cladding/trench (Δ{sub 2}) depth and trench width W{sub t} are investigated. It is shown that some fibre operational parameters, like, fibre bending radius, operating wavelength and fibre length, affect the crosstalk performance. It is found that the crosstalk and its reduction amount are extremely dependent on the values of Δ{sub 1} and Δ{sub 2}. The dispersion characteristics of the cores are investigated for all the proposed core structures and the observed dispersion is found to be about – 6 ps nm{sup −1} km{sup −1} at an operating wavelength of 1550 nm. An ultralow crosstalk (less than –100 dB per 100 km) can be achieved mainly with two proposed core structures (St4 and St5) having a suitably higher values of Δ{sub 1} along with a small core radius for single-mode propagation. The multicore fibre design with many cores (up to 55) is demonstrated to ensure a high transmission capacity. (optical fibres)

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2019

Neutron Imaging With Li-Glass Based Multicore SCIntillating FIber (SCIFI)

The improvement of neutron imaging towards and beyond the microscale is a well-documented need for the iterative characterization and modeling of numerous microstructured X-ray opaque materials. This work presents the recent progress in evaluating a SCIntillating FIber (SCIFI) proof-of-concept towards micron-level thermal neutron radiography. These SCIFIs are composed of 6 Li-enriched silicate glass cores doped with a Ce activator. The cores possess ~8.5 μm diameters and ~10 μm pitch following fiber drawing with a cladding glass into an all-solid multicore fiber. A polished 5 mm × 5 mm array of 100 microstructured multicore SCIFI pixels was fabricated into a 1 mm thick faceplate. The neutron efficiency and light yield of the faceplate are characterized as functions of the 7.38 weight percent of Li 2 O, thickness, and the 70% active volume. It was determined that approximately 39% of a thermal neutron (2 Å) beam can be absorbed by the faceplate. The 6 L i ( n , &#x03B1;<!-- α --> ) t reaction is estimated to produce 7,700 ± 1,000 scintillation photons per event, referencing light collection from 241 Am irradiation of the faceplate. Simulations suggest that on average 17.5 ± 1.4% of these photons will be transported to an end of the fiber array for a thermal beam, with at least 7.2% of that total scintillation light being confined into the fiber cores in which it originated. The SCIFI faceplate was integrated into the Neutron Microscope (NM) at the Pulse OverLap DIffractometer (POLDI) beamline located at the Paul Scherrer Institut to image a Siemens star test object. Processed neutron radiographs acquired with the proof-of-concept faceplate resolved features at a state-of-the-art resolution of 16.1 ± 0.5 μm. The potential for even high resolution designs having smaller pitch or different cladding material is discussed.

47 OTHER INSTRUMENTATION↗
DOE OSTI2020

Dynamic Undervolting to Improve Energy Efficiency on Multicore X86 CPUs

Chip manufacturers introduce redundancy at various levels of CPU design to guarantee correct operation, even for worst-case combinations of non-idealities in process variation and system operating conditions. This redundancy is implemented partly in the form of voltage margins. However, for a wide range of real-world execution scenarios these margins are excessive and merely translate to increased power consumption, hindering the effort towards higher-energy efficiency in both HPC and general purpose computing. Our study on the x86-64 Haswell and Skylake multicore microarchitectures reveals-wide voltage margins, which vary across different microarchitectures, different chip parts of the same microarchitecture, and across different workloads. We find that it is necessary to quantify-voltage margins using multi-threaded and multi-instance workloads, as characterization with single-threaded and single-instance workloads that do not stress the CPU to its full capacity typically identifies overly optimistic margins that lead to errors when applied in realistic program execution scenarios. In addition, we introduce, deploy and evaluate a run-time governor that dynamically reduces the supply voltage of modern multicore x86-64 CPUs. Our governor employs a model that takes as input a set of performance metrics which are directly measurable via performance monitoring counters and have high predictive value for the minimum tolerable supply voltage (V min ), to predict and apply the appropriate reduction for the workload at hand. Compared with the conventional DVFS governor, our approach in this study achieves up to 42 percent energy savings for the Skylake family and 34 percent for the Haswell family for complex, real-world applications.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Nonlinear discrete wavefront shaping for spatiotemporal pulse compression with multicore fibers

Here in this work, we apply an effective discrete phase front focusing method to control the coherent combining and temporal compression of laser pulses by means of nonlinear multicore fibers. We numerically demonstrate the possibility of combining almost entirely the input optical pulses injected in all cores, into the central core of a hexagonal lattice multicore fiber. We investigate the optimal operational conditions for the most effective pulse combining and analyze the influence of a positive input pulse temporal chirp and spatial phase modulation. We demonstrate that a pulse, which has been focused into an arbitrary core of the fiber, also undergoes temporal compression.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

1.2-kW all-fiber Yb-doped multicore fiber amplifier

Here we have demonstrated a record-high 1.2 kW, all-fiber multicore amplifier using a six-core single-mode Yb-doped fiber and a multicore pump-signal combiner (PSC). The output power is limited by the pump power of 1.9 kW. We have developed double-clad six-core fibers and PSCs for this demonstration. Each of the six Yb-doped cores has a 17-µm mode-field diameter (MFD) with a trench index profile and is capable of kW-class operation. The potential power scaling to the 10-kW level in a single amplifier with high brightness should be feasible with advanced thermal management and coherent beam combination.

42 ENGINEERING↗
NASA NTRS2011

Using a Multicore Processor for Rover Autonomous Science

Multicore processing promises to be a critical component of future spacecraft. It provides immense increases in onboard processing power and provides an environment for directly supporting fault-tolerant computing. This paper discusses using a state-of-the-art multicore processor to efficiently perform image analysis onboard a Mars rover in support of autonomous science activities.

Mars↗
NASA NTRS2011

Reliable Multicore Processors for NASA Space Missions

The current trend in commercial processors of moving to many cores (30 to100 and beyond) on a single die poses both an opportunity and a challenge for space based processing. 1 2 The opportunity is to leverage this trend for space application and thus provide an order of magnitude increase in onboard processing capability. The challenge is to provide the requisite reliability in an extremely challenging environment. In this paper, we will discuss the requirements for reliable space based multicore computing and approaches being explored to deliver this capability within NASA's extremely tight power, mass, and cost constraints.

radiation hardening↗
NASA NTRSDate not supplied

A System to Provide Deterministic Flight Software Operation and Maximize Multicore Processing Performance: The Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) Datapath

A method and design are described for a system that processes multiple data streams, utilizing a multicore asymmetric processing architecture, that eliminates data interrupts to the application processors. The design supports a deterministic environment for flight software in NASA’s Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) project. The SPLICE project develops sensor, algorithm, and compute technologies for Precision Landing and Hazard Avoidance (PL&HA) capabilities. The compute technology for SPLICE is the Descent and Landing Computer (DLC). The DLC hosts several SPLICE algorithms with high computational resource requirements that must be executed in a real-time and deterministic manner. The software runs on a custom Single Board Computer (SBC), with a Xilinx Ultrascale+ Multiprocessor System-on-a-Chip (MPSoC). Input data for the flight software is from a variety of sensors, unique with respect to data rate and packet size. A data path between the SPLICE sensors and algorithms is designed to efficiently deliver this data to the flight software using the MPSoC asymmetric processing cores and Field Programmable Gate Array (FPGA) fabric. This is implemented in a manner that isolates the application processors running the flight software from interrupts associated with the input data. By leveraging real-time processors on the MPSoC, and a structure with the appropriate interfaces in the shared memory on the SBC, the flight software can use the full set of application processors. The available utilization for each processor in this set is also maximized for the SPLICE applications, providing a sufficiently deterministic execution environment without the cost and overhead of a real-time operating system.

heterogeneous processing system↗
DOE OSTI2019

Worst crosstalk analysis in heterogeneous and trench assisted heterogeneous multicore fiber for different core counts and layouts

In order to obtain appreciably low worst crosstalk level in high core count multicore fiber, heterogeneous MCF with different core configurations and layouts have been investigated analytically using coupled mode equation. The variations in worst crosstalk behavior with respect to the bending radius, core configurations, core layouts, and outer cladding thickness have been analyzed. Further, the core count dependent variations in worst crosstalk level, core pitch, and peak bending radius in different core layouts have been presented. It has been observed that the selection of core configuration, core layout, and outer cladding thickness have significant impact on the reduction in worst crosstalk level. For example, in 12-core normal-index heterogeneous MCF with SLS structure, the core Configuration 1 can provide the worst crosstalk level reduced by 7.09 dB and 16.92 dB in comparison to the other two core configurations, i.e., Configuration 2, and Configuration 3, respectively. Further, for the same core count with TA Configuration 1, SLS core layout can achieve the reduced worst crosstalk level in comparison with circular ORS and DRS, hexagonal ORS and DRS respectively by 24.62 dB, 25.86 dB, 28.87 dB and 30.64 dB.

36 MATERIALS SCIENCE↗
NASA NTRS2023

A System to Provide Deterministic Flight Software Operation and Maximize Multicore Processing Performance: The Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) Datapath

A method and design are described for a system that processes multiple data streams, utilizing a multicore asymmetric processing architecture, that eliminates data interrupts to the application processors. The design supports a deterministic environment for flight software in NASA’s Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) project. The SPLICE project develops sensor, algorithm, and compute technologies for Precision Landing and Hazard Avoidance (PL&HA) capabilities. The compute technology for SPLICE is the Descent and Landing Computer (DLC). The DLC hosts several SPLICE algorithms with high computational resource requirements that must be executed in a real-time and deterministic manner. The software runs on a custom Single Board Computer (SBC), with a Xilinx Ultrascale+ Multiprocessor System-on-a-Chip (MPSoC). Input data for the flight software is from a variety of sensors, unique with respect to data rate and packet size. A data path between the SPLICE sensors and algorithms is designed to efficiently deliver this data to the flight software using the MPSoC asymmetric processing cores and Field Programmable Gate Array (FPGA) fabric. This is implemented in a manner that isolates the application processors running the flight software from interrupts associated with the input data. By leveraging real-time processors on the MPSoC, and a structure with the appropriate interfaces in the shared memory on the SBC, the flight software can use the full set of application processors. The available utilization for each processor in this set is also maximized for the SPLICE applications, providing a sufficiently deterministic execution environment without the cost and overhead of a real-time operating system.

David K. Rutishauser↗