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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1980

Process development for automated solar cell and module production. Task 4: Automated array assembly

A process sequence which can be used in conjunction with automated equipment for the mass production of solar cell modules for terrestrial use was developed. The process sequence was then critically analyzed from a technical and economic standpoint to determine the technological readiness of certain process steps for implementation. The steps receiving analysis were: back contact metallization, automated cell array layup/interconnect, and module edge sealing. For automated layup/interconnect, both hard automation and programmable automation (using an industrial robot) were studied. The programmable automation system was then selected for actual hardware development.

Source record↗
NASA NTRS1980

A low-cost photovoltaic cell process based on thick film techniques

The low-cost, easily automated processing for solar cell fabrication being developed at Spectrolab for the DOE LSA program is described. These processes include plasma-etching, spray-on diffusion sources and antireflective coating, thick film metallization, aluminum back contacts, laser scribing and ultrasonic soldering. The process sequence has been shown to produce solar cells having 15% conversion efficiency at AM1 which meet the cell fabrication budget required for the DOE 1986 cost goal of $0.70 per peak watt in 1980.

Mardesich, N.↗
NASA NTRS2005

Development of CIGS2 Thin Films on Ultralightweight Flexible Large Area Foil Sunstrates

The development of thin film solar cells is aimed at reducing the costs for photovoltaic systems. Use of thin film technology and thin foil substrate such as 5-mil thick stainless steel foil or 1-mil thick Ti would result in considerable costs savings. Another important aspect is manufacturing cost. Current single crystal technology for space power can cost more than $ 300 per watt at the array level and weigh more than 1 kg/sq m equivalent to specific power of approx. 65 W/kg. Thin film material such as CuIn1-xGaxS2 (CIGS2), CuIn(1-x)Ga(x)Se(2-y)S(y) (CIGSS) or amorphous hydrogenated silicon (a-Si:H) may be able to reduce both the cost and mass per unit area by an order of magnitude. Manufacturing costs for solar arrays are an important consideration for total spacecraft budget. For a medium sized 5kW satellite for example, the array manufacturing cost alone may exceed $ 2 million. Moving to thin film technology could reduce this expense to less than $ 500K. Earlier publications have demonstrated the potential of achieving higher efficiencies from CIGSS thin film solar cells on 5-mil thick stainless steel foil as well as initial stages of facility augmentation for depositing thin film solar cells on larger (6 in x 4 in) substrates. This paper presents the developmental study of achieving stress free Mo coating; uniform coatings of Mo back contact and metallic precursors. The paper also presents the development of sol gel process, refurbishment of selenization/sulfurization furnace, chemical bath deposition (CBD) for n-type CdS and scrubber for detoxification of H2S and H2Se gases.

Dhere, Neelkanth G.↗
NASA NTRS1980

Back surface reflectors for solar cells

Sample solar cells were fabricated to study the effects of various back surface reflectors on the device performance. They are typical 50 micrometers thick, space quality, silicon solar cells except for variations of the back contact configuration. The back surfaces of the sample cells are polished to a mirror like finish, and have either conventional full contacts or grid finger contacts. Measurements and evaluation of various metallic back surface reflectors, as well as cells with total internal reflection, are presented. Results indicate that back surface reflectors formed using a grid finger back contact are more effective reflectors than cells with full back metallization and that Au, Ag, or Cu are better back surface reflector metals than Al.

Chai, A. T.↗
NASA NTRS1980

Screen printing technology applied to silicon solar cell fabrication

The process for producing space qualified solar cells in both the conventional and wraparound configuration using screen printing techniques was investigated. Process modifications were chosen that could be easily automated or mechanized. Work was accomplished to optimize the tradeoffs associated with gridline spacing, gridline definition and junction depth. An extensive search for possible front contact metallization was completed. The back surface field structures along with the screen printed back contacts were optimized to produce open circuit voltages of at least an average of 600 millivolts. After all intended modifications on the process sequence were accomplished, the cells were exhaustively tested. Electrical tests at AMO and 28 C were made before and after boiling water immersion, thermal shock, and storage under conditions of high temperature and high humidity.

Thornhill, J. W.↗
NASA NTRS1994

Planar varactor frequency multiplier devices with blocking barrier

The invention relates to planar varactor frequency multiplier devices with a heterojunction blocking barrier for near millimeter wave radiation of moderate power from a fundamental input wave. The space charge limitation of the submillimeter frequency multiplier devices of the BIN(sup +) type is overcome by a diode structure comprising an n(sup +) doped layer of semiconductor material functioning as a low resistance back contact, a layer of semiconductor material with n-type doping functioning as a drift region grown on the back contact layer, a delta doping sheet forming a positive charge at the interface of the drift region layer with a barrier layer, and a surface metal contact. The layers thus formed on an n(sup +) doped layer may be divided into two isolated back-to-back BNN(sup +) diodes by separately depositing two surface metal contacts. By repeating the sequence of the drift region layer and the barrier layer with the delta doping sheet at the interfaces between the drift and barrier layers, a plurality of stacked diodes is formed. The novelty of the invention resides in providing n-type semiconductor material for the drift region in a GaAs/AlGaAs structure, and in stacking a plurality of such BNN(sup +) diodes stacked for greater output power with and connected back-to-back with the n(sup +) GaAs layer as an internal back contact and separate metal contact over an AlGaAs barrier layer on top of each stack.

Lieneweg, Udo↗
NASA NTRS2008

Making a Back-Illuminated Imager with Back-Side Contact and Alignment Markers

A design modification and a fabrication process that implements the modification have been conceived to solve two problems encountered in the development of back-illuminated, back-sidethinned complementary metal oxide/ semiconductor (CMOS) image-detector integrated circuits. The two problems are (1) how to form metal electrical-contact pads on the back side that are electrically connected through the thickness in proper alignment with electrical contact points on the front side and (2) how to provide alignment keys on the back side to ensure proper registration of backside optical components (e.g., microlenses and/or color filters) with the front-side pixel pattern. The essence of the design modification is to add metal plugs that extend from the desired front-side locations through the thickness and protrude from the back side of the substrate. The plugs afford the required front-to-back electrical conduction, and the protrusions of the plugs serve as both the alignment keys and the bases upon which the back-side electrical-contact pads can be formed.

Pain, Bedabrata↗
NASA NTRS1982

Multi-100 kW: Planar low cost solar array development

The applicability of selected low cost options to solar array blanket design was studied by fabricating representative modules and submitting them to thermal cycle environment. Large area (5.9 x 5.9 cm) solar cells of 3 varieties were purchased: (1) Standard wraparound, (2) Copper contacts substituted for the conventional Titanium-Palladium-Silver, and (3) Standard wraparound except with gridded back contact instead of continuous metallization. The baseline cell was purchased to compare fabrication cost and to serve as a control cell during test evaluation of the other two cells. All cells were assembled into either substrate modules where the cell is individually filtered and welded to an integrated Kapton-copper circuit or into a superstrate configuration with 4 cells jointly adhered to a single sheet of microsheet and then welded to the integrated Kapton-copper circuit. Cell quality, particularly in the metallization of contacts, was less than desired. Problems were encountered with copper metallization in laying down a barrier metal which would ohmically bond to the silicon. The cells received were shunted (sintered) or with low contact pull strength (non-sintered), thus leading to the decision to solder rather than weld the copper cells to the Kapton substrate.

Source record↗
NASA NTRS1985

Front and back polysilicon-contacted silicon solar cells

The first use of a (silicon)/ (heavily doped polysilicon)/ (metal) structure to replace the conventional high-low junction (or back-surface-field, BSF) structure of silicon solar cells is reported. Compared with BSF and back-ohmic-contact control samples, the polysilicon-back solar cells show improvements in red spectral response and open-circuit voltage. Measurement reveals that a decrease in effective surface recombination velocity S is responsible for this improvement. Decreased S results for n-type (Si:As) polysilicon, consistent with past findings for bipolar transistors, and for p-type (Si:B) polysilicon, reported here for the first time. Though the present polysilicon-back solar cells are far from optimal, the results suggest a new class of designs for high efficiency silicon solar cells. Detailed technical reasons are advanced to support this view.

Lindholm, F. A.↗
NASA NTRS1990

Millimeter-wave monolithic diode-grid frequency multiplier

A semiconductor diode structure useful for harmonic generation of millimeter or submillimeter wave radiation from a fundamental input wave is fabricated on a GaAs substrate. A heavily doped layer of n(sup ++) GaAs is produced on the substrate and then a layer of intrinsic GaAs on said heavily doped layer on top of which a sheet of heavy doping (++) is produced. A thin layer of intrinsic GaAs grown over the sheet is capped with two metal contacts separated by a gap to produce two diodes connected back to back through the n(sup ++) layer for multiplication of frequency by an odd multiple. If only one metal contact caps the thin layer of intrinsic GaAs, the second diode contact is produced to connect to the n(sup ++) layer for multiplication of frequency by an even number. The odd or even frequency multiple is selected by a filter. A phased array of diodes in a grid will increase the power of the higher frequency generated.

Maserjian, Joseph↗
NASA NTRS1980

Short-circuit current improvement in thin cells with a gridded back contact

The use of gridded back contact on thin silicon solar cells 50 micrometers was investigated. An unexpected increase in short circuit current of almost 10 percent was experienced for 2 cm x 2 cm cells. Control cells with the standard continuous contact metallization were fabricated at the same time as the gridded back cells with all processes identical up to the formation of the back contact. The gridded back contact pattern was delineated by evaporation of Ti-Pd over a photo-resist mask applied to the back of the wafer; the Ti-Pd film on the controls was applied in the standard fashion in a continuous layer over the back of the cell. The Ti-Pd contacts were similarly applied to the front of the wafer, and the grid pattern on both sides of the cell was electroplated with 8-10 micrometers of silver.

Giuliano, M.↗
NASA NTRS1981

Coplanar back contacts for thin silicon solar cells

The type of coplanar back contact solar cell described was constructed with interdigitated n(+) and p(+) type regions on the back of the cell, such that both contacts are made on the back with no metallization grid on the front. This cell construction has several potential advantages over conventional cells for space use namely, convenience of interconnects, lower operating temperatures and higher efficiency due to the elimination of grid shadowing. However, the processing is more complex, and the cell is inherently more radiation sensitive. The latter problem can be reduced substantially by making the cells very thin (approximately 50 micrometers). Two types of interdigitated back contact cells are possible, the types being dependent on the character of the front surface. The front surface field cell has a front surface region that is of the same conductivity type as the bulk but is more heavily doped. This creates an electric field at the surface which repels the minority carriers. The tandem junction cell has a front surface region of a conductivity type that is opposite to that of the bulk. The junction thus created floats to open circuit voltage on illumination and injects carriers into the bulk which then can be collected at the rear junction. For space use, the front surface field cell is potentially more radiation resistant than the tandem junction cell because the flow of minority carriers (electrons) into the bulk will be less sensitive to the production of recombination centers, particularly in the space charge region at the front surface.

Storti, G.↗
NASA NTRS2009

Alternative Packaging for Back-Illuminated Imagers

An alternative scheme has been conceived for packaging of silicon-based back-illuminated, back-side-thinned complementary metal oxide/semiconductor (CMOS) and charge-coupled-device image-detector integrated circuits, including an associated fabrication process. This scheme and process are complementary to those described in "Making a Back-Illuminated Imager With Back-Side Connections" (NPO-42839), NASA Tech Briefs, Vol. 32, No. 7 (July 2008), page 38. To avoid misunderstanding, it should be noted that in the terminology of imaging integrated circuits, "front side" or "back side" does not necessarily refer to the side that, during operation, faces toward or away from a source of light or other object to be imaged. Instead, "front side" signifies that side of a semiconductor substrate upon which the pixel pattern and the associated semiconductor devices and metal conductor lines are initially formed during fabrication, and "back side" signifies the opposite side. If the imager is of the type called "back-illuminated," then the back side is the one that faces an object to be imaged. Initially, a back-illuminated, back-side-thinned image-detector is fabricated with its back side bonded to a silicon handle wafer. At a subsequent stage of fabrication, the front side is bonded to a glass wafer (for mechanical support) and the silicon handle wafer is etched away to expose the back side. The frontside integrated circuitry includes metal input/output contact pads, which are rendered inaccessible by the bonding of the front side to the glass wafer. Hence, one of the main problems is to make the input/output contact pads accessible from the back side, which is ultimately to be the side accessible to the external world. The present combination of an alternative packaging scheme and associated fabrication process constitute a solution of the problem.

Pain, Bedabrata↗
NASA NTRS2011

CMOS Imager Has Better Cross-Talk and Full-Well Performance

A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.

Pain, Bedabrata↗
NASA NTRS1978

Thin silicon solar cell performance characteristics

Refined techniques for surface texturizing, back surface field and back surface reflector formation were evaluated for use with shallow junction, single-crystal silicon solar cells. Each process was characterized individually and collectively as a function of device thickness and bulk resistivity. Among the variables measured and reported are open circuit voltage, short circuit current and spectral response. Substantial improvements were obtained by the utilization of a low cost aluminum paste process to simultaneously remove the unwanted n(+) diffused region, form the back surface field and produce an ohmic contact metallization. The highly effective BSF which results from applying this process has allowed fabrication of cells 0.05 mm thick with initial outputs as high as 79.5 mW/4 sq cm (28 C, AM0) and superior electron radiation tolerance. Cells of 0.02 mm to 0.04 mm thickness have been fabricated with power to mass ratios well in excess of 2 watts per gram.

Gay, C. F.↗
NASA NTRS1983

Investigation of accelerated stress factors and failure/degradation mechanisms in terrestrial solar cells

Results of an ongoing research program into the reliability of terrestrial solar cells are presented. Laboratory accelerated testing procedures are used to identify failure/degradation modes which are then related to basic physical, chemical, and metallurgical phenomena. In the most recent tests, ten different types of production cells, both with and without encapsulation, from eight different manufacturers were subjected to a variety of accelerated tests. Results indicated the presence of a number of hitherto undetected failure mechanisms, including Schottky barrier formation at back contacts and loss of adhesion of grid metallization. The mechanism of Schottky barrier formation is explained by hydrogen, formed by the dissociation of water molecules at the contact surface, diffusing to the metal semiconductor interface. This same mechanism accounts for the surprising increase in sensitivity to accelerated stress conditions that was observed in some cells when encapsulated.

Lathrop, J. W.↗
NASA NTRS1984

MOD silver metallization for photovoltaics

Photovoltaic cells require back side metallization and a collector grid system on the front surface. Both front and back surface metallizations should have good adhesion, low contact resistance, low sheet resistance, long term stability, and their deposition methods should not degrade the n-p junction. Advantages and disadvantages of different deposition methods are discussed.

Vest, G. M.↗
NASA NTRS1987

Solar Cels With Reduced Contact Areas

Efficiency of silicon solar cells increased about 20 percent using smaller metal-contact area on silicon at front and back of each cell. Reduction in contact area reduces surface recombination velocity under contact and thus reduces reverse saturation current and increases opencircuit voltage..

Daud, T.↗