Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “memory spaces”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1974

A multiprocessor computer simulation model employing a feedback scheduler/allocator for memory space and bandwidth matching and TMR processing

A computer simulation model for a multiprocessor computer is developed that is useful for studying the problem of matching multiprocessor's memory space, memory bandwidth and numbers and speeds of processors with aggregate job set characteristics. The model assumes an input work load of a set of recurrent jobs. The model includes a feedback scheduler/allocator which attempts to improve system performance through higher memory bandwidth utilization by matching individual job requirements for space and bandwidth with space availability and estimates of bandwidth availability at the times of memory allocation. The simulation model includes provisions for specifying precedence relations among the jobs in a job set, and provisions for specifying precedence execution of TMR (Triple Modular Redundant and SIMPLEX (non redundant) jobs.

Bradley, D. B.↗
DOE OSTI2023

Dynamic kernel memory space allocation

A processing unit includes one or more processor cores and a set of registers to store configuration information for the processing unit. The processing unit also includes a coprocessor configured to receive a request to modify a memory allocation for a kernel concurrently with the kernel executing on the at least one processor core. The coprocessor is configured to modify the memory allocation by modifying the configuration information stored in the set of registers. In some cases, initial configuration information is provided to the set of registers by a different processing unit. The initial configuration information is stored in the set of registers prior to the coprocessor modifying the configuration information.

Gutierrez, Anthony↗
NASA NTRS2003

Quantum Search in Hilbert Space

A proposed quantum-computing algorithm would perform a search for an item of information in a database stored in a Hilbert-space memory structure. The algorithm is intended to make it possible to search relatively quickly through a large database under conditions in which available computing resources would otherwise be considered inadequate to perform such a task. The algorithm would apply, more specifically, to a relational database in which information would be stored in a set of N complex orthonormal vectors, each of N dimensions (where N can be exponentially large). Each vector would constitute one row of a unitary matrix, from which one would derive the Hamiltonian operator (and hence the evolutionary operator) of a quantum system. In other words, all the stored information would be mapped onto a unitary operator acting on a quantum state that would represent the item of information to be retrieved. Then one could exploit quantum parallelism: one could pose all search queries simultaneously by performing a quantum measurement on the system. In so doing, one would effectively solve the search problem in one computational step. One could exploit the direct- and inner-product decomposability of the unitary matrix to make the dimensionality of the memory space exponentially large by use of only linear resources. However, inasmuch as the necessary preprocessing (the mapping of the stored information into a Hilbert space) could be exponentially expensive, the proposed algorithm would likely be most beneficial in applications in which the resources available for preprocessing were much greater than those available for searching.

Zak, Michail↗
NASA NTRS2000

Implementation of Ferroelectric Memories for Space Applications

Ferroelectric random access semiconductor memories (FeRAMs) are an ideal nonvolatile solution for space applications. These memories have low power performance, high endurance and fast write times. By combining commercial ferroelectric memory technology with radiation hardened CMOS technology, nonvolatile semiconductor memories for space applications can be attained. Of the few radiation hardened semiconductor manufacturers, none have embraced the development of radiation hardened FeRAMs, due a limited commercial space market and funding limitations. Government funding may be necessary to assure the development of radiation hardened ferroelectric memories for space applications.

Philpy, Stephen C.↗
NASA NTRS2001

Future Development of Dense Ferroelectric Memories for Space Applications

The availability of high density, radiation tolerant, nonvolatile memories is critical for space applications. Ferroelectric memories, when fabricated with radiation hardened complementary metal oxide semiconductors (CMOS), can be manufactured and packaged to provide high density replacements for Flash memory, which is not radiation tolerant. Previous work showed ferroelectric memory cells to be resistant to single event upsets and proton irradiation, and ferroelectric storage capacitors to be resistant to neutron exposure. In addition to radiation hardness, the fast programming times, virtually unlimited endurance, and low voltage, low power operation make ferroelectric memories ideal for space missions. Previously, a commercial double level metal 64-kilobit ferroelectric memory was presented. Although the capabilities of radiation hardened wafer fabrication facilities lag behind those of the most modern commercial wafer fabrication facilities, several paths to achieving radiation tolerant, dense ferroelectric memories are emerging. Both short and long term solutions are presented in this paper. Although worldwide major semiconductor companies are introducing commercial ferroelectric memories, funding limitations must be overcome to proceed with the development of high density, radiation tolerant ferroelectric memories.

Philpy, Stephen C.↗
DOE OSTI2024

Developing And Scaling an OpenFOAM Model to Study Turbulent Flow in a HFIR Coolant Channel

Improving the understanding of how computational fluid dynamics (CFD) direct numerical simulations (DNS) of flows in the High Flux Isotope Reactor (HFIR) perform when run in parallel using the high performance computing (HPC) platform Summit at the Oak Ridge Leadership Computing Facility (OLCF) is of particular importance to boost the computational tools used to support HFIR conversion to low enriched fuel (LEU). Evaluation of scaling performance was driven by the increasing importance of graphics processing unit (GPU) usage in HPC, which is becoming the standard for modern supercomputers such as Summit. The desired results are to obtain a strong positive correlation between the computational resources dedicated to a problem and the relative speed-up of the simulation in comparison to a benchmark. This capability will allow substantially improvement in HFIR flow analytical capabilities, specifically when predicting turbulence properties at high Reynolds numbers. The study leverages previous simulation results performed with code PHASTA (finite element) on HPC platforms Cori (NERSC) and Theta (ALCF) [1] with computing options provided in the computing platform OpenFOAM (finite volume) at OLCF. Transitioning from PHASTA to OpenFOAM will (1) eliminate dependence on third-party software for mesh generation and manipulation, (2) reduce resource needs by employing modern architectures, and (3) build expertise for future modeling of HFIR-specific problems like heat transfer in involute geometry, entrance effects, flow structure in channel corners, and so on—all important issues when defining the available thermal margins in the transition to LEU. CPUs and GPUs differ significantly in their architecture and utilization, as discussed in the literature [2]. The most important differences are in the approach to computations and their memory. A single GPU contains a large quantity of cores, enabling it to perform with a much higher throughput than a CPU, but execution requires a different approach. GPU codes execute instructions using the Single-Instruction Multiple-Thread (SIMT) approach in which a single instruction is used for groups of threads called warps. A warp typically consists of 32 threads which must execute the same set of instructions, although on separate threads. Alternately, a CPU has far fewer cores that are much more flexible in their operation, excelling at quickly performing more complex serial computations. This is why GPUs have greater throughput when properly utilized. The second important difference is seen when comparing their memory spaces. Limited memory allocations and CPU–GPU communications cause a significant bottleneck in GPU-accelerated programs. Further study was required to properly take advantage of GPU resources. A comprehensive analysis of code performance and the model-specific features of turbulence constitutes the core of this work. In this study, a DNS simulation of HFIR channel turbulence was performed with the finite volume CFD code OpenFOAM v2112 and CUDA v11.0 on Red Hat Enterprise Linux v8.2. The OpenFOAM installation had AMGx integrated to enable GPU acceleration and utilizes the PETSc4FOAM library. The computational resources and the problem size were scaled on CPU and CPU + GPU architectures to gain a better understanding of the performance of a DNS problem on modern computing hardware. The study aimed to analyze the scaling of the code exclusively on CPUs and then to examine the scaling of the codes with GPU acceleration enabled. Scaling studies included CPU and GPU acceleration on a mesh of varying resolution to analyze the impact of problem size relative to computational resources. In the course of preparing the GPU configuration on Summit, mainly using the AMGX solvers, difficulties were encountered stemming from constant changes resulting from extensive ongoing development activities and the changing environment. This resulted in the inability to complete the GPU portion of the work. The code was compiled and tested, but production runs to assess acceleration were not performed because the used discretional compute time allocation expired as year-end approached. The Summit HPC platform is scheduled for decommissioning in 2024, making it unattractive for future use with Nvidia-based GPUs. Therefore, the work will be moved onto NERSC machines in FY24. An application was prepared and submitted, and sufficient node-hours were awarded to continue the research in the next calendar year. This report summarizes work performed thus far, which mostly focused on CPU OpenFOAM computing.

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗
NASA NTRS2009

On Nibbles and Bytes: The Conundrum of Memory for Space Systems - NASA Electronic Parts and Packaging (NEPP) and Efforts in Memories

Radiation requirements and trends. TID: 1) >90% of NASA applications are < 100 krads-Si in piecepart requirements. a) Many commercial devices (NVM and SDRAMs) meet or come close to this. b) Charge pump TID tolerance has improved an order magnitude over the last 10 years. 2) There are always a few programs with higher level needs and, of course, defense needs SEL: 1) Prefer none or rates that are considered low risk. a) Latent damage is a bear to deal with. 2) As we re packing cells tighter and even with lower Vdd, we re seeing SEL on commercial devices regularly (<90nm). a) Often in power conversion, I/O, or control areas. SEU: 1) It s not the bit errors, it s the SEFIs errors that are the biggest issues. a) Scrubbing concerns for risk, power, speed.

LaBel, Kenneth A.↗
DOE OSTI2020

A view into FleCSI [Slides]

FleCSI is largely based around sharing of memory spaces. FleCSI facilitates parallel execution and sharing of memory across memory spaces. Execute() transforms sender-side data structures into receiver-side data structures.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Design Space Exploration of Emerging Memory Technologies for Machine Learning Applications

Memory design space exploration methods study memory systems’ performances and limitations before implementation. The computer memory design space has grown exponentially because of the enormous growth of memory types, memory controllers, and application software. Computer simulators are commonly used for memory design space exploration. However, complex memory simulations take an enormous amount of time. Hence, in this paper, we proposed a machine learning-based design space exploration method for dynamic random-access memory and non-volatile memory systems. We applied our method to the CosmoGAN and LeNet applications to predict the following six memory response parameters: (i) bandwidth, (ii) power, (iii) average latency, (iv) average total latency, (v) memory reads, and (vi) memory writes. Our experimental results show that machine learning models can predict memory response parameter values faster than simulations. We used support vector machine, random forest, and gradient boosting machine learning models. We observed that the support vector machine provides better performance for bandwidth, average latency, and average total latency. The random forest model works better for memory reads and writes. The gradient boosting model provides superior prediction performance for power. We provide a detailed discussion on learning curve characteristics, error analysis, and memory type recommendation.

Hasan, S M Shamimul↗
NASA NTRS1980

Proton upsets in LSI memories in space

Two types of large scale integrated dynamic random access memory devices were tested and found to be subject to soft errors when exposed to protons incident at energies between 18 and 130 MeV. These errors are shown to differ significantly from those induced in the same devices by alphas from an Am-241 source. There is considerable variation among devices in their sensitivity to proton-induced soft errors, even among devices of the same type. For protons incident at 130 MeV, the soft error cross sections measured in these experiments varied from 10 to the -8th to 10 to the -6th sq cm/proton. For individual devices, however, the soft error cross section consistently increased with beam energy from 18-130 MeV. Analysis indicates that the soft errors induced by energetic protons result from spallation interactions between the incident protons and the nuclei of the atoms comprising the device. Because energetic protons are the most numerous of both the galactic and solar cosmic rays and form the inner radiation belt, proton-induced soft errors have potentially serious implications for many electronic systems flown in space.

Mcnulty, P. J.↗
NASA NTRS2002

SEU evaluation of FeRAM memories for space applications

SEU cross-sections were obtained for two different FeRAM memories: The 64 kbit and 256 kbit Ramtron FeRAM and the Hynix 64 kbit device. The devices were seen to have latch-up characteristics typical of commercial CMOS. Also, errors in the memory were also seen from heavy ion irradiation.

SEU FeRAM ion irradiation↗
DOE OSTI2020

Consistent Space Runtime (CSPACER) v1.0

This software provides a runtime for communication-bound applications, especially with irregular communication patterns. The target programming abstraction for the runtime is the space consistency model, which defines consistency guarantees at the granularity of memory spaces. This model has relaxed consistency semantics that enables a wide range of runtime optimizations. The runtime leverages threading to accelerate communication primitives, especially collective operations. It also allows efficient pipelining of communication operations and enable constructing a consistent state of multiple unordered communication activities targeting a memory space. The runtime uses a reduced API design that decomposes complex communication primitives in traditional general-purpose runtime into a sequence of simpler steps. To improve the productivity of using this runtime, we provide communication patterns commonly used for regular scientific computing applications and irregular data analytics. These communication patterns offer skeletons for the integration with application computation to allow efficient overlap.

Ibrahim, Khaled↗
NASA NTRS1988

Orthogonal patterns in binary neural networks

A binary neural network that stores only mutually orthogonal patterns is shown to converge, when probed by any pattern, to a pattern in the memory space, i.e., the space spanned by the stored patterns. The latter are shown to be the only members of the memory space under a certain coding condition, which allows maximum storage of M=(2N) sup 0.5 patterns, where N is the number of neurons. The stored patterns are shown to have basins of attraction of radius N/(2M), within which errors are corrected with probability 1 in a single update cycle. When the probe falls outside these regions, the error correction capability can still be increased to 1 by repeatedly running the network with the same probe.

Baram, Yoram↗