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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

New Total-Ionizing-Dose Resistant Data Storing Technique for NAND Flash Memory

This paper describes a new non-charge-based data storing technique in NAND flash memory called watermark that encodes read-only data in the form of physical properties of flash memory cells. Unlike traditional charge-based data storing method in flash memory, the proposed technique is resistant to total ionizing dose (TID) effects. To evaluate its resistance to irradiation effects, we analyze data stored in several commercial single-level-cell (SLC) flash memory chips from different vendors and technology nodes. These chips are irradiated using a Co-60 gamma-ray source array for up to 100 krad(Si) at Sandia National Laboratories. Experimental evaluation performed on a flash chip from Samsung shows that the intrinsic bit error rate (BER) of watermark increases from 0.8% for TID = 0 krad(Si) to 1% for TID = 100 krad(Si). Conversely, the BER of charge-based data stored on the same chip increases from 0% at TID = 0 krad(Si) to 1.5% at TID = 100 krad(Si). Overall, the results imply that the proposed technique may potentially offer significant improvements in data integrity relative to traditional charge-based data storage for very high radiation (TID > 100 krad(Si)) environments. These gains in data integrity relative to the charge-based data storage are useful in radiation-prone environments, but they come at the cost of increased write times and higher BERs before irradiation.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Total-Ionizing-Dose Effects on Long-term Data Retention Characteristics of Commercial 3-D NAND Memories

This article evaluates the data retention characteristics of irradiated multi-level cell (MLC) 3-D NAND flash memories. We irradiate the memory chips by a Co-60 gamma-ray source for up to 50 krad(Si) and then write a random data pattern on the irradiated chip to find its retention characteristics. The experimental results show that the data retention property of the irradiated chips is significantly degraded compared to the un-irradiated ones. We evaluate two independent strategies to improve the data retention characteristics of the irradiated chips. Furthermore, the first method involves high-temperature annealing of the irradiated chip while the second method suggests pre-programming the memory modules before deploying them in radiation-prone environments.

3-D NAND flash↗
DOE OSTI2022

Tolerating memory stack failures in multi-stack systems

Memory management circuitry and processes operate to improve reliability of a group of memory stacks, providing that if a memory stack or a portion thereof fails during the product's lifetime, the system may still recover with no errors or data loss. A front-end controller receives a block of data requested to be written to memory, divides the block into sub-blocks, and creates a new redundant reliability sub-block. The sub-blocks are then written to different memory stacks. When reading data from the memory stacks, the front-end controller detects errors indicating a failure within one of the memory stacks, and recovers corrected data using the reliability sub-block. The front-end controller may monitor errors for signs of a stack failure and disable the failed stack.

Mappouras, Georgios↗
DOE OSTI2024

Comparison of ML-Based Proxy Modeling Strategies: Lessons Learned from the SMART Initiative

Teams of researchers on Task 5 of the SMART project have developed a variety of modeling architectures to predict subsurface behavior during carbon injection and post-injection periods. One important part of this task was to compare the candidate approaches in terms of accuracy, reliability, speed, and memory use, all using a common set of metrics and visualizations for an “apples to apples” comparison. Dr. Jared Schuetter will share the details of this task, the results that were obtained, and the lessons learned.

Schuetter, Jared↗
DOE OSTI2024

Understanding GPU Memory Corruption at Extreme Scale: The Summit Case Study

GPU memory corruption and in particular double-bit errors (DBEs) remain one of the least understood aspects of HPC system reliability. Albeit rare, their occurrences always lead to job termination and can potentially cost thousands of node-hours, either from wasted computations or as the overhead from regular checkpointing needed to minimize the losses. As supercomputers and their components simultaneously grow in scale, density, failure rates, and environmental footprint, the efficiency of HPC operations becomes both an imperative and a challenge. We examine DBEs using system telemetry data and logs collected from the Summit supercomputer, equipped with 27,648 Tesla V100 GPUs with 2nd-generation high-bandwidth memory (HBM2). Using exploratory data analysis and statistical learning, we extract several insights about memory reliability in such GPUs. We find that GPUs with prior DBE occurrences are prone to experience them again due to otherwise harmless factors, correlate this phenomenon with GPU placement, and suggest manufacturing variability as a factor. On the general population of GPUs, we link DBEs to short- and long-term high power consumption modes while finding no significant correlation with higher temperatures. We also show that the workload type can be a factor in memory’s propensity to corruption.

Oles, Vlad↗
DOE OSTI2023

Towards generic memory forensic framework for programmable logic controllers

A Programmable Logic Controller (PLC) is a microprocessor-based controller that is used to automate physical processes in critical infrastructure and various other industries and manufacturing sectors. Initially, PLCs were completely isolated from the Internet, and cyber security was not incorporated at the time of development. The introduction of industry 4.0 and the evolution of ICS systems to communicate over public IP addresses from the Internet enhanced productivity and efficiency, but Internet connectivity exposed the systems and their vulnerabilities, which led to an increase in cyber attacks. When a system is sabotaged/compromised, security analysts need to get to the root cause of the attack as quickly as possible to recover the system. To do so, memory forensic analysis is critical to provide a unique insight into the run-time memory activities and extract a reliable source of evidence. In this paper, we analyze the memory structure of the Schneider Electric Modicon M221 PLC. To build a memory profile, we reverse engineer the communication protocol and conduct differential analysis to gain knowledge about the structure of the memory and the low-level representation of control logic instructions. We then identify dynamic and static memory regions by modifying different project fields and conducting differential analysis, which allows us to identify boundaries of critical memory structures and extract important forensic artifacts that can be found in the memory. The Python implementation of the memory profile can help reduce the time and effort required for manual analysis in case of cyber incident or system failure.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Variation-Resilient FeFET-Based In-Memory Computing Leveraging Probabilistic Deep Learning

Reliability issues stemming from device level nonidealities of nonvolatile emerging technologies like ferroelectric field-effect transistors (FeFETs), especially at scaled dimensions, cause substantial degradation in the accuracy of in-memory crossbar-based AI systems. Here, in this work, we present a variation-aware design technique to characterize the device level variations and to mitigate their impact on hardware accuracy employing a Bayesian neural network (BNN) approach. An effective conductance variation model is derived from the experimental measurements of cycle-to-cycle (C2C) and device-to-device (D2D) variations performed on FeFET devices fabricated using 28 nm high-k metal gate technology. The variations were found to be a function of different conductance states within the given programming range, which sharply contrasts earlier efforts where a fixed variation dispersion was considered for all conductance values. Such variation characteristics formulated for three different device sizes at different read voltages were provided as prior variation information to the BNN to yield a more exact and reliable inference. Near-ideal accuracy for shallow networks (MLP5 and LeNet models) on the MNIST dataset and limited accuracy decline by ~3.8%–16.1% for deeper AlexNet models on CIFAR10 dataset under a wide range of variations corresponding to different device sizes and read voltages, demonstrates the efficacy of our proposed device-algorithm co-design technique.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs

Ferroelectric random access memory (FeRAM) is a promising candidate for energy-efficient nonvolatile memory, particularly for logic-in-memory and compute-in-memory (CIM) applications. Among the available cell architectures, One-Transistor–n-Capacitor (1T-nC) and two-transistor–n-capacitor (2T-nC) FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study of these two architectures under both dimensional scaling ( XY/Z shrinkage) and vertical integration (increasing stacked capacitors per cell). Using technology computer-aided design (TCAD) and circuit-level simulations, we analyze how scaling impacts ferroelectric capacitance, parasitic coupling, and floating-node (FN) dynamics, which together dictate sense margin (SM) and read stability. A key mitigation strategy—floating unselected capacitors—is applied to both architectures, effectively decoupling the SM from the number of stacked capacitors and enabling tractable analysis across scaling regimes. Results show that 1T-nC suffers more from charge sharing with the bitline (BL), while 2T-nC benefits from transistor isolation and stronger low-voltage sensing at the cost of increased area. By systematically evaluating these behaviors across scaling directions, this work establishes the reliability trade-offs of 1T-nC and 2T-nC cells and provides design guidelines for high-density, vertically integrated FeRAM systems.

1T-nC↗
DOE OSTI2022

Persistent memory as an effective alternative to random access memory in metagenome assembly

Abstract Background The assembly of metagenomes decomposes members of complex microbe communities and allows the characterization of these genomes without laborious cultivation or single-cell metagenomics. Metagenome assembly is a process that is memory intensive and time consuming. Multi-terabyte sequences can become too large to be assembled on a single computer node, and there is no reliable method to predict the memory requirement due to data-specific memory consumption pattern. Currently, out-of-memory (OOM) is one of the most prevalent factors that causes metagenome assembly failures. Results In this study, we explored the possibility of using Persistent Memory (PMem) as a less expensive substitute for dynamic random access memory (DRAM) to reduce OOM and increase the scalability of metagenome assemblers. We evaluated the execution time and memory usage of three popular metagenome assemblers (MetaSPAdes, MEGAHIT, and MetaHipMer2) in datasets up to one terabase. We found that PMem can enable metagenome assemblers on terabyte-sized datasets by partially or fully substituting DRAM. Depending on the configured DRAM/PMEM ratio, running metagenome assemblies with PMem can achieve a similar speed as DRAM, while in the worst case it showed a roughly two-fold slowdown. In addition, different assemblers displayed distinct memory/speed trade-offs in the same hardware/software environment. Conclusions We demonstrated that PMem is capable of expanding the capacity of DRAM to allow larger metagenome assembly with a potential tradeoff in speed. Because PMem can be used directly without any application-specific code modification, these findings are likely to be generalized to other memory-intensive bioinformatics applications.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2026

A Survey on the Expanding Scope and Interdisciplinary Opportunities for Processing-in-Memory Techniques

Processing-in-Memory (PIM) is emerging as a practical path to overcome the limitations of traditional von Neumann architectures. At its core, PIM systems implement computing primitives such as logic operations and multiply-accumulate acceleration through compute-in-memory, near-memory processing, or hybrid designs. The role of memory cells varies widely across technologies, acting as inputs, outputs, or analog accumulators through bit-lines and sense amplifiers. This diversity creates trade-offs in precision, bandwidth, latency, and programmability, making it difficult to build a unified understanding on the progress of the field. In this survey, we organize recent advances of PIM into three areas. First, we discuss the progress on the architectural optimizations of PIM and its integration with both DRAM and emerging non-volatile memories. Second, we examine how PIM is being used to accelerate key computing domains, including generative AI workloads and high-performance kernels, along with new approaches. Third, we highlight the growing adoption of PIM in computational sciences, where it is being applied to solve interdisciplinary problems such as genome analysis, mRNA quantification, mass spectrometry, quantum circuit simulation, wave modeling, and secure computation. Finally, we synthesize the major challenges that continue to slow PIM adoption, including manufacturing constraints, power delivery, thermal reliability, data consistency, runtime and memory-management coordination, and the difficulty of building portable software abstractions without sacrificing commercial viability. This work provides an updated, structured perspective on PIM’s potential across computing and computational sciences and the barriers that must be solved for it to reach its full impact.

Asifuzzaman, Kazi [Oak Ridge National Laboratory (↗
DOE OSTI2024

Selective consolidation of learning and memory via recall-gated plasticity

In a variety of species and behavioral contexts, learning and memory formation recruits two neural systems, with initial plasticity in one system being consolidated into the other over time. Moreover, consolidation is known to be selective; that is, some experiences are more likely to be consolidated into long-term memory than others. Here, we propose and analyze a model that captures common computational principles underlying such phenomena. The key component of this model is a mechanism by which a long-term learning and memory system prioritizes the storage of synaptic changes that are consistent with prior updates to the short-term system. This mechanism, which we refer to as recall-gated consolidation, has the effect of shielding long-term memory from spurious synaptic changes, enabling it to focus on reliable signals in the environment. We describe neural circuit implementations of this model for different types of learning problems, including supervised learning, reinforcement learning, and autoassociative memory storage. These implementations involve synaptic plasticity rules modulated by factors such as prediction accuracy, decision confidence, or familiarity. We then develop an analytical theory of the learning and memory performance of the model, in comparison to alternatives relying only on synapse-local consolidation mechanisms. We find that recall-gated consolidation provides significant advantages, substantially amplifying the signal-to-noise ratio with which memories can be stored in noisy environments. We show that recall-gated consolidation gives rise to a number of phenomena that are present in behavioral learning paradigms, including spaced learning effects, task-dependent rates of consolidation, and differing neural representations in short- and long-term pathways.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2024

Selective consolidation of learning and memory via recall-gated plasticity

In a variety of species and behavioral contexts, learning and memory formation recruits two neural systems, with initial plasticity in one system being consolidated into the other over time. Moreover, consolidation is known to be selective; that is, some experiences are more likely to be consolidated into long-term memory than others. Here, we propose and analyze a model that captures common computational principles underlying such phenomena. The key component of this model is a mechanism by which a long-term learning and memory system prioritizes the storage of synaptic changes that are consistent with prior updates to the short-term system. This mechanism, which we refer to as recall-gated consolidation, has the effect of shielding long-term memory from spurious synaptic changes, enabling it to focus on reliable signals in the environment. We describe neural circuit implementations of this model for different types of learning problems, including supervised learning, reinforcement learning, and autoassociative memory storage. These implementations involve synaptic plasticity rules modulated by factors such as prediction accuracy, decision confidence, or familiarity. We then develop an analytical theory of the learning and memory performance of the model, in comparison to alternatives relying only on synapse-local consolidation mechanisms. We find that recall-gated consolidation provides significant advantages, substantially amplifying the signal-to-noise ratio with which memories can be stored in noisy environments. We show that recall-gated consolidation gives rise to a number of phenomena that are present in behavioral learning paradigms, including spaced learning effects, task-dependent rates of consolidation, and differing neural representations in short- and long-term pathways.

Lindsey, Jack W. (ORCID:0000000309307327)↗
DOE OSTI2023

Suppressing Structural Relaxation in Nanoscale Antimony to Enable Ultralow‐Drift Phase‐Change Memory Applications

Abstract Phase‐change random‐access memory (PCRAM) devices suffer from pronounced resistance drift originating from considerable structural relaxation of phase‐change materials (PCMs), which hinders current developments of high‐capacity memory and high‐parallelism computing that both need reliable multibit programming. This work realizes that compositional simplification and geometrical miniaturization of traditional GeSbTe‐like PCMs are feasible routes to suppress relaxation. While to date, the aging mechanisms of the simplest PCM, Sb, at nanoscale, have not yet been unveiled. Here, this work demonstrates that in an optimal thickness of only 4 nm, the thin Sb film can enable a precise multilevel programming with ultralow resistance drift coefficients, in a regime of ≈10 −4 –10 −3 . This advancement is mainly owed to the slightly changed Peierls distortion in Sb and the less‐distorted octahedral‐like atomic configurations across the Sb/SiO 2 interfaces. This work highlights a new indispensable approach, interfacial regulation of nanoscale PCMs, for pursuing ultimately reliable resistance control in aggressively‐miniaturized PCRAM devices, to boost the storage and computing efficiencies substantially.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2025

Enhancing quantum memory lifetime with measurement-free local error correction and reinforcement learning

Reliable quantum computation requires systematic identification and correction of errors that occur and accumulate in quantum hardware. To diagnose and correct such errors, standard quantum error-correcting protocols utilize global error information across the system obtained by mid-circuit readout of ancillary qubits. We investigate circuit-level error-correcting protocols that are measurement-free and based on local error information. Such a local error correction (LEC) circuit consists of faulty multi-qubit gates to perform both syndrome extraction and ancilla-controlled error removal. We develop and implement a reinforcement learning framework that takes a fixed set of faulty gates as inputs and outputs an optimized LEC circuit. To evaluate this approach, we quantitatively characterize an extension of logical qubit lifetime by a noisy LEC circuit. For the two-dimensional (2D) classical Ising model and four-dimensional toric code, our optimized LEC circuit performs better at extending a memory lifetime compared with a conventional LEC circuit based on Toom's rule in a subthreshold gate error regime. We further show that such circuits can be used to reduce the rate of mid-circuit readouts to preserve a 2D toric code memory. Lastly, we discuss the application of the LEC protocol on dissipative preparation of quantum states with topological phases.

74 ATOMIC AND MOLECULAR PHYSICS↗
DOE OSTI2025

Learning efficient erasure protocols for an underdamped memory

Here we apply evolutionary reinforcement learning to a simulation model to identify efficient time-dependent erasure protocols for a physical realization of a 1-bit memory using an underdamped mechanical cantilever. We show that these protocols, when applied to the cantilever in the laboratory, are considerably more efficient than our best hand-designed protocols. The learned protocols allow reliable high-speed erasure by minimizing the heating of the memory during its operation. More generally, the combination of methods used here opens the door to the rational design of efficient protocols for various physics applications.

74 ATOMIC AND MOLECULAR PHYSICS↗
DOE OSTI2026

ALD-Derived WO 3– x Leads to Nearly Wake-Up-Free Ferroelectric Hf 0.5 Zr 0.5 O 2 at Elevated Temperatures

Breaking the memory wall in advanced computing architectures will require complex 3D integration of emerging memory materials such as ferroelectrics─either within the back-end-of-line (BEOL) of CMOS front-end processes or through advanced 3D packaging technologies. Achieving this integration demands that memory materials exhibit high thermal resilience, with the capability to operate reliably at elevated temperatures, such as 125°C, due to the substantial heat generated by front-end transistors. However, silicon-compatible HfO 2 -based ferroelectrics tend to exhibit antiferroelectric-like behavior in this temperature range, accompanied by a more pronounced wake-up effect, posing significant challenges to their thermal reliability. Here, we report that by introducing a thin tungsten oxide (WO 3–x ) layer─known as an oxygen reservoir─and carefully tuning its oxygen content, ultrathin Hf 0.5 Zr 0.5 O 2 (5 nm) films can be made robust against the ferroelectric-to-antiferroelectric transition at elevated temperatures. This approach not only minimizes polarization loss in the pristine state but also effectively suppresses the wake-up effect, reducing the required wake-up cycles from 10 5 to only 10 at 125°C, a qualifying temperature for back-end memory integrated with front-end logic, as defined by the JEDEC standard. First-principles density functional theory (DFT) calculations reveal that WO 3 enhances the stability of the ferroelectric orthorhombic phase (o-phase) at elevated temperatures by increasing the tetragonal-to-orthorhombic phase energy gap and promoting favorable phonon mode evolution, thereby supporting o-phase formation under both thermodynamic and kinetic constraints.

36 MATERIALS SCIENCE↗
DOE OSTI2025

VA EDH Advanced Software Pipeline Framework Report: Enhancing Automation and Scalability

The VA Environmental Determinants of Health (EDH) Advanced Software Pipeline Framework is designed to enhance the efficiency, scalability, and security of geospatial data processing workflows. This framework integrates modern data orchestration and containerization technologies, including Prefect for workflow automation, Docker for containerization, and PostgreSQL/PostGIS for geospatial data storage and analysis. It ensures standardized, reproducible, and automated data processing, supporting VA objectives related to substance use risk assessment and recovery research. The pipeline addresses key scalability and performance challenges through horizontal and vertical scaling, high-performance computing (HPC) integration, parallel processing, task caching, and dynamic resource allocation. These optimizations improve throughput and reduce latency, allowing the system to efficiently manage large and complex datasets. Additionally, security and compliance measures—such as data encryption (SSL), Role-Based Access Control (RBAC), and adherence to GDPR and HIPAA standards—safeguard sensitive information throughout data transmission and storage. A key implementation of this framework includes the automation of shelter list geolocation workflows, ensuring that up-to-date data is readily available for VA decision-making. Lessons learned from this project include the transition from in-memory processing to incremental storage writes, improving resource management and reliability. Future enhancements aim to expand automation, integrate AI-driven anomaly detection, and incorporate high-performance computing resources. This framework provides a scalable, secure, and adaptable solution for managing geospatial datasets, reinforcing the VA’s ability to support clinical and strategic initiatives through data-driven decision-making.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Uncertainty-aware Continuous Implicit Neural Representations for Remote Sensing Object Counting

Many existing object counting methods rely on density map estimation (DME) of the discrete grid representation by decoding extracted image semantic features from designed convolutional neural networks (CNNs). Relying on discrete density maps not only leads to information loss dependent on the original image resolution, but also has a scalability issue when analyzing high-resolution images with cubically increasing memory complexity. Furthermore, none of the existing methods can offer reliable uncertainty quantification (UQ) for the derived count estimates. To overcome these limitations, we design UNcertainty-aware, hypernetwork-based Implicit neural representations for Counting (UNIC) to assign probabilities and the corresponding counting confidence over continuous spatial coordinates. We derive a sampling-based Bayesian counting loss function and develop the corresponding model training algorithm. UNIC outperforms existing methods on the Remote Sensing Object Counting (RSOC) dataset with reliable UQ and improved interpretability of the derived count estimates. Our code is available at https://github.com/SiyuanXu-tamu/UNIC.

97 MATHEMATICS AND COMPUTING↗