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Novel interconnect technologies leveraging low melting temperature solders, such as multiwire interconnects, are being deployed in photovoltaic (PV) modules for improved reliability through interconnect redundancy and lower thermal loads during interconnection and lamination. However, the equivalency of standardized accelerated testing to field conditions has not yet been established for these emerging technologies. In this study, the thermomechanical fatigue resistance of low temperature solder alloys is investigated and compared to that of conventional SnPb to assess the acceleration behavior of these alloys. While InSn is shown to have sufficient thermomechanical fatigue resistance on the order of that of SnPb, these results indicate Sn–Bi alloys may have poor thermomechanical fatigue resistance at field conditions. The results also show that Sn–Bi alloys have thermal cycling acceleration factors of less than one. This indicates that the standardized accelerated thermal cycling test, such as that in IEC 61215, will produce misleading results for Sn–Bi alloys and that unique testing is required for this PV module architecture. Though accelerated thermal cycling may be a meaningful qualification test for SnPb solder joints, these results suggest that mechanical loading may be a more appropriate test for Sn–Bi multiwire interconnects. This is due to the distinct processing and geometry of multiwire interconnects which may allow for mechanical, rather than strictly metallurgical interconnections.
Nuclear fusion is an enticing alternative to current sources of energy, with multilayered Rare-Earth Barium Copper Oxide (REBCO) coated conductors deemed pivotal in the race toward fully realized, commercially viable, and magnetic confinement fusion reactors. In this study, we simulated the ion spectrum expected to evolve from REBCO's nickel-based Hastelloy C-276 substrate and copper stabilizer in an affordable robust compact-like reactor. We then emulated this gas production through helium implantation to investigate changes in materials and superconducting properties. Our results revealed that the substrate and stabilizer are capable of producing protons energetic enough to recoil throughout the tape thickness in appreciable doses, and alphas energetic enough to deposit 7.54 × 1014 ions/cm2 or 50.1 helium appm in the superconducting layer over a 30-year reactor lifetime. The superconducting layer of SuperPower® tapes exhibited at least double the swelling rate of the other major layers, and both SuperPower and Fujikura Ltd. tapes displayed microstructural changes in the REBCO layer not observed in isotropic metals. For the estimated lifetime fluence, the Fujikura tapes showed a ∼1 K reduction in critical temperature and a 32% degradation in critical current for compact reactor-relevant conditions (16 T, 20 K). Nuclear transmutation, low-temperature solder implantations, gas-ion evolution, the influence of gas production on vortex dynamics, and other related considerations are also discussed.
Two generations of multiwire modules were studied under dynamic mechanical loading (DML) with in-situ differential conductance (dG) and electroluminescence (EL) imaging. Energy-dispersive x-ray spectroscopy (EDS) was used to identity the solder alloys. The earlier generation module was found to use an In-based solder alloy, and the current generation a Bi-based alloy. The earlier generation module degraded significantly under DML with increasing resistance, while the current generation module did not demonstrate degradation under DML. Atomic force microscopy scratch testing was used to probe the wear resistance of each solder alloy. These results indicate that current multiwire designs may have higher mechanical durability than earlier generations.
Two generations of multiwire modules were studied under dynamic mechanical loading (DML). The earlier generation module was found to use an In-based solder alloy, and the current generation a Bi-based alloy. The earlier generation module degraded significantly under DML with increasing resistance, while the state-of-the-art module did not demonstrate degradation under DML. The degradation in the earlier module was attributed to damage at the solder-gridline interfaces. Atomic force microscopy scratch testing estimated the wear resistance of each solder alloy to assess susceptibility to degradation. Bi-based alloys appear to be more wear resistant than In-based alloys, consistent with the DML results. These results indicate that current multiwire designs may have higher mechanical durability than earlier generations.
A low temperature cofired ceramic substrate comprises a plurality of dielectric layers, at least one inner conductor layer, a plurality of bond pads, and a solder mask. The dielectric layers are formed from ceramic material and placed one on top of another to form a stack. The inner conductor is formed from electrically conductive paste and positioned on an upper surface of at least one inner dielectric layer. The bond pads are positioned on an outer surface of the stack. Each bond pad is formed from a plurality of conductive sublayers of thin film metal stacked one on top of another, with each conductive sublayer being formed from a different metal. The solder mask is positioned on the same outer surface of the stack as the bond pads and includes a plurality of openings, with each opening exposing at least a portion of one of the bond pads.
The sintering processing–structure–property relationship of a multiscale silver materials is investigated: microparticles with nanofeatures, particularly on their three-dimensional (3D) morphology. The target application is to replace conventional lead-based solders in advanced electronic manufacturing. Unlike lead-based solders, silver powders are suited to satisfy increasingly demanding mechanical, electrical, and thermal requirements, meanwhile being free of health effect. Sintering the material at a low temperature and without applied pressure are desirable conditions, which results in a preferred use of silver nanoparticles, as nanofeatures have higher driving force to sinter with the decrease in particle size. However, nanosized powders present potential health/environmental effects. To address the trade-off between the benefits and shortcomings of nano-versus microparticles, this work studies a novel multiscale silver paste, namely micron-sized powders with nanosized features. To get quantitative 3D visualization of micro- and nanoscale features, ptychographic X-ray computed nanotomography is applied. The correlations between conditions (thermal aging, pressure, and substrate metallization), mechanical properties, and morphological parameters are established. Finally, using novel 3D X-ray nanoimaging technique, it is demonstrated that one can design multiscale materials while balancing complex demands required in advanced electronics manufacturing and research directions in materials design and characterization.
We demonstrate the fabrication of fiber-optic Fabry–Perot interferometer (FPI) temperature sensors by bonding a small silicon diaphragm to the tip of an optical fiber using low melting point glass powders heated by a 980 nm laser on an aerogel substrate. The heating laser is delivered to the silicon FPI using an optical fiber, while the silicon temperature is being monitored using a 1550 nm white-light system, providing localized heating with precise temperature control. The use of an aerogel substrate greatly improves the heating efficiency by reducing the thermal loss of the bonding parts to the ambient environment. A desirable temperature for bonding can be achieved with relatively small heating laser power. The bonding process is carried out in an open space at room temperature for convenient optical alignment. The precise temperature control ensures minimum perturbation to the optical alignment and no induced thermal damage to the optical parts during the bonding process. For demonstration, we fabricated a low-finesse and high-finesse silicon FPI sensor and characterized their measurement resolution and temperature capability. The results show that the fabrication method has a good potential for high-precision fabrication of fiber-optic sensors.
Power electronics packages typically comprise a dielectric substrate bonded to a metal layer and attached to heat sinks using a low-thermal-conductivity solder. These multiple layers increase the effective thermal resistance of the package and are responsible for package failures under cyclic thermal loads. Bonding the aluminum nitride dielectric layer (AlN) directly to a low coefficient of thermal expansion (CTE) aluminum silicon carbide (AlSiC) cold plate using copper-aluminum (Cu-Al) transient liquid phase (TLP) bonding has been shown to improve the mechanical reliability of the power electronic packages while making the package more compact by bringing the cooling solutions closer to the devices. This study aims to characterize the Cu-Al bonds formed during the TLP bonding of AlSiC with three different power electronics substrates: pure aluminum nitride (AlN), aluminum (DBA), and copper (DBC). The material compositions and microstructures of the bonds were analyzed using scanning electron microscopy (SEM), x-ray spectroscopy (EDS), confocal scanning acoustic microscopy (C-SAM), and x-ray diffraction (XRD). ..alpha..-Al solid compound was identified as the dominant phase in AlN-AlSiC and Al-AlSiC, with a notable presence of SiC particles. In contrast, three intermetallic phases - ..theta..-CuAl2, ..eta..-CuAl, and ..gamma..'- Cu9Al4 - were observed in the Cu-AlSiC bond. A computational solid-state diffusion model was developed to predict the intermetallic compounds (IMCs) formed during Cu-Al TLP bonding in each system, which supported the observation that an initial Cu volume fraction of 20 % in the material layers produced a final bond composition of >95 % Al with minimal IMC growth. However, increased Cu concentrations produced higher concentration gradients, leading to increased growth of IMCs, Kirkendall voids, and interstitial cracks.
High temperature packaging technologies are a necessity for high temperature capable devices. SAC305 solder has an operational limit of 174°C imposed by creep effects which aligns well with current junction temperature limits of 175°C. Wide band gap semiconductor materials have the potential to reach junction temperatures of up to 800°C that are not currently attainable with significant reliability. Capitalizing on this potential will requires substrates and attachments that can operate well beyond the current 175°C standard. Silver sintering pastes have received widespread interest as a high temperature attachment alternative. However, the process requires high pressure bonding in an inert environment to achieve acceptable bond quality. Transient liquid phase (TLP) sintering is capable of good bond quality without pressure requirements but suffers from low thermal conductivity and only slightly reduced cost compared to silver sintering. SAC305 solder contains the same constituent materials for TLP as available copper-tin TLP sintering paste. By introducing engineered surface structures into the bond, intermetallic formation can be accelerated producing a bond similar to TLP sintering but in an ambient environment and for reduced cost. While this process has been demonstrated, it has not yet been optimized. Currently bonds are formed using a 75 μm stencil on substrate surface structures 24 μm tall, covering 19% of the bonding area. The process takes about 4 hours not including the formation of surface structures. Here, this study will center on the effects of stencil thickness and coating methods. Samples will be analyzed by scanning acoustic microscopy, die shear testing and cross sectional scanning acoustic microscopy.
Solders with superconducting transitions around 4K are useful in low magnetic field environments for AC current leads or in electrical and mechanical bonds. Accurate knowledge of these solders’ superconducting properties is essential for improving high precision experiments. We have measured the electrical resistance of five commercially-available eutectic or near-eutectic solders: 50%Sn-50%Pb, 60%Sn-40%Pb, 60%Sn-40%Pb-0.3%Sb, 52%In-48%Sn, and 96.5%Sn-3.5%Ag, down to 2.3K and in applied magnetic fields from 0 to 0.1 T . We report critical temperatures T c (B), 90%–10% transition widths ΔT c , and zero-temperature critical fields B c,0 . Our best candidate for low-loss AC current wiring in low fields is 50%Sn-50%Pb, which has a zero-field T c,0 = 7.1K (with ΔT c = 0.6 K), and remained high at T c (0.1 T) = 6.9K (ΔT c = 0.6K ). We also report, for the first time, T c and B c of 60%Sn-40%Pb-0.3%Sb and B c,0 of 96.5%Sn-3.5%Ag. Our T c,0 - 3.31K (ΔT c = 0.08K) for 96.5%Sn-3.5%Ag disagrees with a widely adopted value.
Work in the project was spread across 4 main themes:1) Improved Understanding of Why Cracks Form and Cause Degradation in Solar Cells: We developed a finite element model which correlated well with experimental determined deflection vs load profiles and which predicted stress profiles vs load level and temperature. These profiles helped to guide brace designs and showed the high stress levels seen in the silicon near the interconnect wire locations as the temperature is cooled below -30C, likely forming "invisible" microcracks. Experiments showed how for polymer backsheet modules, a brief exposure to such low temperatures made modules extremely sensitive to propagation of these microcracks at relatively low load levels, and how thicker and softer encapsulant helped to reduce this crack sensitivity. We showed for some modules that most cracks that are seen under loading had their origin at short, hard to see, V-cracks from soldering damage, and how the shunting from cells with high densities of cracks reduces energy delivery more than Pmax. 2) Improved Durability Testing Methods With Respect to Cracked Cells: We lobbied the PV community throughout the project that IEC 61215 was insufficient to probe the sensitivity of module Pmax degradation due to cracks in that in did not have a test leg that included a crack creation step (static loading) followed by a crack opening step (cyclic loading and/or thermal cycling). We published extensively on how pre- existing cracks opened up with cyclic loading. The new IEC TS 63209-1 ED1 test sequence now include our recommendations, and this should lead to improved module designs and reduced risk for investors. We also published recommendations for a new "Cold Climate Test" sequence to probe the sensitivity of modules to degradation from short microcracks formed when modules see temperatures below -30C followed by front side loading. We participated in several USTAG meetings related to cracked cells, EL testing, and mechanical load testing and provided input to the group to improve new standards under consideration. We also showed how the act of performing an EL test can affect the test results due to heating from the injected current. 3) New Module Designs and Related Manufacturing Methods & Equipment: We demonstrated reduced crack sensitivity on encapsulated cell coupons the benefits of building protective compressive stress into the cells by laminating them in a bent state and then allowing the coupon to flatten out after lamination. Our attempts to scale this to the module level with a more manufacturable sequence did not demonstrate the same positive effects, but we hope that others will follow up with other variations on this bent lamination or bent cooling concept to make more durable modules. 4) New Module Mounting Designs: We explored a range of bracing concepts which pressed on the backsheet to slightly bow the glass outward and place cells in a state of protective compressive stress and to reduce the deflection under front side loads. These successfully reduced cell cracking and crack opening, but high static loads permanently deformed cost-effective braces, after which they provided little benefit. We settled on an elegant & effective solution – the RailPad, where lightweight bracing elements are placed between the mounting rail(s) and the backsheet, and the existing strength of the rails is used to prevent module deflection under load. New construction and retrofit designs were made, and test sites were implemented in FL and MA. We applied for RailPad patent protection.
Uniaxial stress is used to detwin samples of orthorhombic iron based superconductors to study their intrinsic electronic anisotropy. Here we describe the development of a new detwinning setup enabling variable-load stress-detwinning with easy sample mounting/dismounting without the need to re-solder the contacts. It enables the systematic study of the anisotropy evolution as a function of an external parameter when the sample is modified between the measurements. In our case, the external parameter is the dose of 2.5 MeV electron irradiation at low temperature. We illustrate the approach by studying resistivity anisotropy in single crystals of Ba 1-x K x Fe 2 As 2 at x =0.25 where the much discussed unusual re-entrance of tetragonal C 4 phase, C 4 → C 2 → C 4 , is observed on cooling. With the described technique we found a significant anisotropy increase in C 2 phase after electron irradiation with dose of 2.35 C/cm 2 .
Abstract A low AC loss Rare Earth Barium Copper Oxide (REBCO) cable, based on the VIPER cable technology has been developed by Commonwealth Fusion Systems for use in high field, REBCO based tokamaks. The new cable is composed of partitioned and transposed copper ‘petals’ shaped to fit together in a circular pattern with each petal containing a REBCO tape stack and insulated from each other to reduce AC losses. A stainless steel jacket adds mechanical robustness—also serving as a vessel for solder impregnation—while a tube runs through the middle for cooling purposes. Additionally, fiber optic sensors are placed under the tape stacks for quench detection. To qualify this design, a series of experiments were conducted as part of the SPARC tokamak Central Solenoid Model Coil program—to retire the risks associated with full scale, fast ramping, high flux HTS Central Solenoid (CS) and Poloidal Field (PF) coils for tokamak fusion power plants and net energy demonstrators. These risk study and risk reduction experiments include (1) AC loss measurement and model validation in the range of ~5 T/s, (2) an IxB electromagnetic loading of over 850 kN/m at the cable level and up to 300 kN/m at the stack level, (3) a transverse compression resilience of over 350 MPa, (4) manufacturability at tokamak relevant speeds and scales, (5) cable to cable joint performance, (6) fiber optic based quench detection speed, accuracy, and feasibility, and (7) overall winding pack integration and magnet assembly. The result is a cable technology, now referred to as PIT VIPER, with AC losses that measure fifteen times lower (at ~5 T/s) than its predecessor technology; a 2% or lower degradation of critical current (Ic) at high IxB electromagnetic loads; no detectable Ic degradation up to 570 MPa of transverse compression on the cable unit cell; end to end magnet manufacturing, consistently producing Ic values within 7% of the model prediction; cable to cable joint resistances at 20 K on the order of ~15 nΩ; and fast, functional quench detection capabilities that do not involve voltage taps. This cable technology will be tested comprehensively in a Central Solenoid Model Coil to prove its readiness for compact, high field tokamak operation.
Electroluminescence (EL) imaging is a powerful tool used to identify defects in photovoltaic solar cells. Typically, this type of characterization is performed in the dark using a current injection that equals short-circuit current measured at standard test conditions (STC). Restricting imaging to such a temperature range limits the information obtained about the module and cells. However, it is not trivial to develop a tool that would allow for EL imaging to be performed under a wider range of temperatures. Here we demonstrate an in situ EL imaging capability developed within an environmental chamber that allows for control of sample temperatures between –40 and 90 °C. Additionally, we demonstrate EL imaging of 4-cell mini-modules (MiMo) under front-side mechanical loading. A Raspberry Pi-connected camera with short-pass filter removed is used for EL imaging. The camera is low-cost with a small form-factor, appropriate for use in a harsh, enclosed environment. The camera is installed within a thermally isolating housing mounted within the environmental chamber. Three example cases are given for MiMos that exhibit various forms of degradation including solder fatigue and cell cracking. It is shown that by measuring at conditions above and below STC, different behaviors may be identified. In some cases, restricting characterization to STC may lead to a failure to detect damage existing in the sample.
This project aimed to develop technologies that can potentially enable free-standing thin (<80 μm) wafer in today’s manufacturing lines with high production yield, and thereby reduce capex barriers of silicon photovoltaics cells and modules. One of the major benefits is that thin wafer dramatically reduces the amount of polysilicon required. As a result, it can lead to reduction in the capital expenditures associated with polysilicon refining and wafer fabrication, which together are more than half of the total capital expenditure to manufacture Si PV module. We focused our efforts on developing the tools needed to enable high yield fabrication of wafer, cell, and module with thin silicon wafers. However, as the wafer thickness reduces, the major challenge is that wafer breakage increases significantly. Three technological areas were explored in this project to improve the production yield of the silicon wafer, namely detection of edge cracks via dark-field near-infrared (NIR) scattering; (2) wafer handling using controlled temperature profiles; (3) manufacturable low-stress cell interconnection for multiwire. First, the formation of wafer cracks in submillimeter length is one of the reasons that causes wafer breakages. Crack detection tools are needed to enable us to locate and track the wafer crack during manufacturing, so that we can improve the process to reduce initialization. The state-of-the-art crack detection technique cannot fulfill the need for measuring submillimeter edge cracks detrimental for thin wafers. The prototype developed in this project demonstrates the scanning of microcracks near wafer edges. With a semi-automatic laboratory setup, the submillimeter cracks were reliably detected near the edges in multi-Si wafers. The smallest detectable crack is 200 µm in length in slow scans; and submillimeter cracks are detected in high-throughput scans at the scan speed of >0.5 m/s, which is compatible with the inline detection of a manufacturing line at least 1 sec/wafer. This detection limit is a significant advancement in comparison to the benchmarked industrial tool. Second, wafer handling with the well-controlled temperature profile was thought to be the solution to reduce crack initiation and propagation during the manufacturing. However, without crack detection being widely adopted in production line, we did not find a strong industrial pull toward this technology. We did an initial literature survey and then diverted our efforts to the other tasks. Third, the innovation on low-stress multi-wire interconnection tackles a fundamental problem in the standard interconnection scheme. The standard over-under “zig-zag” interconnection induces a significant amount of stress into the soldering point on the cell whenever PV module is under stress, e.g., thermal cycling, transportation, and installation. Therefore, the interconnection process was re-designed in this project to allow for significant movement between adjacent solar cells, e.g., due to thermal expansion, without building up stresses on the solar cells or solder joints. The new interconnection method with the cross-connect wire also simplifies the tabbing and stringing process by replacing the standard over-under method with an off-cell interconnect from top to bottom. A manual tabbing and stringing tool for this new process was prototyped in the lab to demonstrate the fabrication of this new interconnection design. During the test with brass sheets as our “testing cells”, it was found that the mechanical cycling test only broke the interconnection after more than 50,000 cycles, which is equivalent to more than 130 years of the day-and-night thermal cycles. Lastly, throughout the project, we continuously analyzed the PV market with techno-economic analysis to identify the opportunity for thin Si adoption. Even though the drastic cost reduction has already happened in the past five years, our analysis results indicated that we can still save quite significantly in both manufacturing cost and factory capex, Particularly, in order to grow the PV manufacturing capacity to multi-terawatt level, reducing the thickness of silicon wafer is one of the most effective ways to quickly reduce factory capex, and sustain the high growth rate. The technologies developed in this project are readily available to provide some assistances in tackling the production yield problem.
Landslides are a global and frequent natural hazard, affecting many communities and infrastructure networks. Technological solutions are needed for long-term, large-scale condition monitoring of infrastructure earthworks or natural slopes. However, current instruments for slope stability monitoring are often costly, require a complex installation process and/or data processing schemes, or have poor resolution. Wireless sensor networks comprising low-power, low-cost sensors have been shown to be a crucial part of landslide early warning systems. Here, we present the development of a novel sensing approach that uses linear arrays of three-axis accelerometers for monitoring changes in sensor inclination, and thus the surrounding soil’s deformation. By combining these deformation measurements with depth-resolved temperature measurements, we can link our data to subsurface thermal–hydrological regimes where relevant. In this research, we present a configuration of cascaded I2C sensors that (i) have ultra-low power consumption and (ii) enable an adjustable probe length. From an electromechanical perspective, we developed a novel board-to-board connection method that enables narrow, semi-flexible sensor arrays and a streamlined assembly process. The low-cost connection method relies on a specific FR4 printed circuit board design that allows board-to-board press fitting without using electromechanical components or solder connections. The sensor assembly is placed in a thin, semi-flexible tube (inner diameter 6.35 mm) that is filled with an epoxy compound. The resulting sensor probe is connected to an AA-battery-powered data logger with wireless connectivity. We characterize the system’s electromechanical properties and investigate the accuracy of deformation measurements. Our experiments, performed with probes up to 1.8 m long, demonstrate long-term connector stability, as well as probe mechanical flexibility. Furthermore, our accuracy analysis indicates that deformation measurements can be performed with a 0.390 mm resolution and a 95% confidence interval of ±0.73 mm per meter of probe length. This research shows the suitability of low-cost accelerometer arrays for distributed soil stability monitoring. In comparison with emerging low-cost measurements of surface displacement, our approach provides depth-resolved deformation, which can inform about shallow sliding surfaces.
This project describes the modeling process to design the packaging and heat exchanger for a half-bridge wide-bandgap (WBG) power semiconductor module. The module uses two silicon carbide, metal-oxide-semiconductor field-effect transistor (MOSFET) devices per switch position that are soldered to an aluminum nitride, direct-bond copper (DBC) substrate. A baseplate cooling configuration (e.g., no thermal grease) is used along with a water-ethylene glycol, jet-impingement-style heat exchanger. The heat exchanger was designed to be fabricated using prototyping equipment from the National Renewable Energy Laboratory, complies with automotive standards (for minimal channel sizes, flow rates, and coolant), and considers reliability aspects (i.e., erosion/corrosion). Device-scale computational fluid dynamics (CFD) is used first to design the slot jet impingement cooling configuration and compute the effective heat transfer coefficient (HTC) of the concept. The computed HTCs are then used as boundary conditions for a finite element study to optimize the package geometry (e.g., device layout and baseplate thickness) to minimize thermal resistance and minimize temperature variation between the module's four devices. Finally, a fluid manifold is designed to generate the slot jets and cool the devices. Module-scale CFD predicts a relatively low junction-to-fluid thermal resistance of 16.7 mm2 K/W, a 1.4 degrees C temperature variation between devices, and a total pressure drop of 5,860 Pa (0.85 psi) for the design. The thermal resistance of the module design is about 67% lower than the 2015 BMW i3 power electronics/modules thermal resistance.