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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Lattice-Matched Semiconductor Layers on Single Crystalline Sapphire Substrate

SiGe is an important semiconductor alloy for high-speed field effect transistors (FETs), high-temperature thermoelectric devices, photovoltaic solar cells, and photon detectors. The growth of SiGe layer is difficult because SiGe alloys have different lattice constants from those of the common Si wafers, which leads to a high density of defects, including dislocations, micro-twins, cracks, and delaminations. This innovation utilizes newly developed rhombohedral epitaxy of cubic semiconductors on trigonal substrates in order to solve the lattice mismatch problem of SiGe by using trigonal single crystals like sapphire (Al2O3) as substrate to give a unique growth-orientation to the SiGe layer, which is automatically controlled at the interface upon sapphire (0001). This technology is different from previous silicon on insulator (SOI) or SGOI (SiGe on insulator) technologies that use amorphous SiO2 as the growth plane. A cubic semiconductor crystal is a special case of a rhombohedron with the inter-planar angle, alpha = 90 deg. With a mathematical transformation, all rhombohedrons can be described by trigonal crystal lattice structures. Therefore, all cubic lattice constants and crystal planes (hkl) s can be transformed into those of trigonal crystal parameters. These unique alignments enable a new opportunity of perfect lattice matching conditions, which can eliminate misfit dislocations. Previously, these atomic alignments were thought to be impossible or very difficult. With the invention of a new x-ray diffraction measurement method here, growth of cubic semiconductors on trigonal crystals became possible. This epitaxy and lattice-matching condition can be applied not only to SiGe (111)/sapphire (0001) substrate relations, but also to other crystal structures and other materials, including similar crystal structures which have pointgroup rotational symmetries by 120 because the cubic (111) direction has 120 rotational symmetry. The use of slightly miscut (less than plus or minus 10 deg.) sapphire (0001) substrate can be used to improve epitaxial relationships better by providing attractive atomic steps in the epitaxial process.

Choi, Sang↗
NASA NTRS1991

Flange Correction For Metal-To-Metal Contacts

Improved mathematical model provides correction for flange effect in estimating resistance of square contact between two metal layers from standard four-terminal measurements. Extended version of one developed previously for contact between metal layer and semiconductor layer, wherein flange effect important in semiconductor layer only. Here flange effect in both metal layers significant. Interfacial resistances extracted more accurately.

Lieneweg, Udo↗
NASA NTRS1998

Buried Porous Silicon-Germanium Layers in Monocrystalline Silicon Lattices

Monocrystalline semiconductor lattices with a buried porous semiconductor layer having different chemical composition is discussed and monocrystalline semiconductor superlattices with a buried porous semiconductor layers having different chemical composition than that of its monocrystalline semiconductor superlattice are discussed. Lattices of alternating layers of monocrystalline silicon and porous silicon-germanium have been produced. These single crystal lattices have been fabricated by epitaxial growth of Si and Si-Ge layers followed by patterning into mesa structures. The mesa structures are strain etched resulting in porosification of the Si-Ge layers with a minor amount of porosification of the monocrystalline Si layers. Thicker Si-Ge layers produced in a similar manner emitted visible light at room temperature.

Fathauer, Robert W.↗
NASA NTRS2017

340 Ghz Multipixel Transceiver

A multi-pixel terahertz transceiver is constructed using a stack of semiconductor layers that communicate using vias defined within the semiconductor layers. By using a stack of semiconductor layers, the various electrical functions of each layer can be tested easily without having to assemble the entire transceiver. In addition, the design allows the production of a transceiver having pixels set 10 mm apart.

Chattopadhyay, Goutam↗
NASA NTRS2004

Reproducible Growth of High-Quality Cubic-SiC Layers

Semiconductor electronic devices and circuits based on silicon carbide (SiC) are being developed for use in high-temperature, high-power, and/or high-radiation conditions under which devices made from conventional semiconductors cannot adequately perform. The ability of SiC-based devices to function under such extreme conditions is expected to enable significant improvements in a variety of applications and systems. These include greatly improved high-voltage switching for saving energy in public electric power distribution and electric motor drives; more powerful microwave electronic circuits for radar and communications; and sensors and controls for cleaner-burning, more fuel-efficient jet aircraft and automobile engines.

Neudeck, Philip G.↗
NASA NTRS2006

Highly Efficient Multilayer Thermoelectric Devices

Multilayer thermoelectric devices now at the prototype stage of development exhibit a combination of desirable characteristics, including high figures of merit and high performance/cost ratios. These devices are capable of producing temperature differences of the order of 50 K in operation at or near room temperature. A solvent-free batch process for mass production of these state-of-the-art thermoelectric devices has also been developed. Like prior thermoelectric devices, the present ones have commercial potential mainly by virtue of their utility as means of controlled cooling (and/or, in some cases, heating) of sensors, integrated circuits, and temperature-critical components of scientific instruments. The advantages of thermoelectric devices for such uses include no need for circulating working fluids through or within the devices, generation of little if any noise, and high reliability. The disadvantages of prior thermoelectric devices include high power consumption and relatively low coefficients of performance. The present development program was undertaken in the hope of reducing the magnitudes of the aforementioned disadvantages and, especially, obtaining higher figures of merit for operation at and near room temperature. Accomplishments of the program thus far include development of an algorithm to estimate the heat extracted by, and the maximum temperature drop produced by, a thermoelectric device; solution of the problem of exchange of heat between a thermoelectric cooler and a water-cooled copper block; retrofitting of a vacuum chamber for depositing materials by sputtering; design of masks; and fabrication of multilayer thermoelectric devices of two different designs, denoted I and II. For both the I and II designs, the thicknesses of layers are of the order of nanometers. In devices of design I, nonconsecutive semiconductor layers are electrically connected in series. Devices of design II contain superlattices comprising alternating electron-acceptor (p)-doped and electron-donor (n)-doped, nanometer- thick semiconductor layers.

Boufelfel, Ali↗
NASA NTRS2004

Self-contained sub-millimeter wave rectifying antenna integrated circuit

The invention is embodied in a monolithic semiconductor integrated circuit in which is formed an antenna, such as a slot dipole antenna, connected across a rectifying diode. In the preferred embodiment, the antenna is tuned to received an electromagnetic wave of about 2500 GHz so that the device is on the order of a wavelength in size, or about 200 microns across and 30 microns thick. This size is ideal for mounting on a microdevice such as a microrobot for example. The antenna is endowed with high gain in the direction of the incident radiation by providing a quarter-wavelength (30 microns) thick resonant cavity below the antenna, the cavity being formed as part of the monolithic integrated circuit. Preferably, the integrated circuit consists of a thin gallium arsenide membrane overlying the resonant cavity and supporting an epitaxial Gallium Arsenide semiconductor layer. The rectifying diode is a Schottky diode formed in the GaAs semiconductor layer and having an area that is a very small fraction of the wavelength of the 2500 GHz incident radiation. The cavity provides high forward gain in the antenna and isolation from surrounding structure.

Siegel, Peter H.↗
NASA NTRS1988

Experiences in extraction of contact parameters from process-evaluation test-structures

Six-terminal-contact test structures are introduced for characterizing ohmic contacts between a metal and a heavily doped semiconductor layer. Specifically, the six-terminal test structure supplies the additional information needed in order to calculate the transmission length and eventual corrections to the characteristic resistance per unit width due to finite contact length. The essential feature of this test structure is a square contact with four taps in the lower (semiconductor) layer. Every other one of these taps is used for current injection ('front'). From the voltage drop at the opposite tap and the side taps, the 'end' resistance and the 'side' resistances are calculated. The test structures are shown to give valuable information complementary to the common front resistance measurements. The interfacial resistivity is obtained directly after proper correction for flange effects.

Lieneweg, Udo↗
NASA NTRS1994

Nucleation, growth, and strain relaxation of lattice-mismatched 3-5 semiconductor epitaxial layers

We have investigated the early stages of evolution of highly strained 2-D InAs layers and 3-D InAs islands grown by metal-organic chemical vapor deposition (MOCVD) on (100) and (111)B GaAs substrates. The InAs epilayer/GaAs substrate combination has been chosen because the lattice-mismatch is severe (approximately 7.2 percent), yet these materials are otherwise very similar. By examining InAs-on-GaAs composites instead of the more common In(x)Ga(1-x)As alloy we remove an additional degree of freedom (x) and thereby simplify data interpretation. A matrix of experiments is described in which the MOCVD growth parameters - susceptor temperature, Thin flux, and AsH3 flux - have been varied over a wide range. Scanning electron microscopy, atomic force microscopy, transmission electron microscopy, and electron microprobe analysis have been employed to observe the thin film surface morphology. In the case of 3-D growth, we have extracted activation energies and power-dependent exponents that characterize the nucleation process. As a consequence, optimized growth conditions have been identified for depositing approximately 250 A thick (100) and (111)B oriented InAs layers with relatively smooth surfaces. Together with preliminary data on the strain relaxation of these layers, the above results on the evolution of thin InAs films indicate that the (111)B orientation is particularly promising for yielding lattice-mismatched films that are fully relaxed with only misfit dislocations at the epilayer/substrate interface.

Welser, R. E.↗
NASA NTRS1994

Nucleation, Growth, and Strain Relaxation of Lattice-Mismatched III-V Semiconductor Epitaxial Layers

We have investigated the early stages of evolution of highly strained 2-D InAs layers and 3-D InAs islands grown by metal-organic chemical vapor deposition (MOCVD) on (100) and (111) B GaAs substrates. The InAs epilayer / GaAs substrate combination has been chosen because the lattice-mismatch is severe (approx. 7.20%), yet these materials are otherwise very similar. By examining InAs-on-GaAs composites Instead of the more common In(x)Ga(1-x)As alloy, we remove an additional degree of freedom (x) and thereby simplify data interpretation. A matrix of experiments is described in which the MOCVD growth parameters -- susceptor temperature, TMIn flux, and AsH3 flux -- have been varied over a wide range. Scanning electron microscopy, atomic force microscopy, transmission electron microscopy, and electron microprobe analysis have been employed to observe the thin film surface morphology. In the case of 3-D growth, we have extracted activation energies and power-dependent exponents that characterize the nucleation process. As a consequence, optimized growth conditions have been identified for depositing approx. 250 A thick (100) and (111)B oriented InAs layers with relatively smooth surfaces. Together with preliminary data on the strain relaxation of these layers, the above results on the evolution of thin InAs films indicate that the (111)B orientation is particularly promising for yielding lattice-mismatched films that are fully relaxed with only misfit dislocations at the epilayer / substrate interface.

Welser, R. E.↗
NASA NTRS1990

Tunable quantum well infrared detector

A novel infrared detector (20, 20', 20), is provided, which is characterized by photon-assisted resonant tunneling between adjacent quantum wells (22a, 22b) separated by barrier layers (28) in an intrinsic semiconductor layer (24) formed on an n.sup.+ substrate (26), wherein the resonance is electrically tunable over a wide band of wavelengths in the near to long infrared region. An n.sup.+ contacting layer (34) is formed over the intrinsic layer and the substrate is n.sup.+ doped to provide contact to the quantum wells. The detector permits fabrication of arrays (30) (one-dimensional and two-dimensional) for use in imaging and spectroscopy applications.

Maserjian, Joseph↗
NASA NTRS2011

Epitaxial Growth of Cubic Crystalline Semiconductor Alloys on Basal Plane of Trigonal or Hexagonal Crystal

Hetero-epitaxial semiconductor materials comprising cubic crystalline semiconductor alloys grown on the basal plane of trigonal and hexagonal substrates, in which misfit dislocations are reduced by approximate lattice matching of the cubic crystal structure to underlying trigonal or hexagonal substrate structure, enabling the development of alloyed semiconductor layers of greater thickness, resulting in a new class of semiconductor materials and corresponding devices, including improved hetero-bipolar and high-electron mobility transistors, and high-mobility thermoelectric devices.

Park, Yeonjoon↗
NASA NTRS1990

Layered Internal-Photoemission Sensor

High quantum efficiency achieved without multiple layer contacts. Proposed infrared sensor based on photoemission from multiple layers of metal silicide sandwiched between layers of silicon. Suitable for use in focal-plane arrays. Layered internal-photoemission sensor has positive/intrinsic/negative structure modified by inclusion of layers or islands of metal silicide. Holes photo-excited from silicide regions and swept to detection by reverse-bias electric field in intrinsic silicon. Easier to make because internal layers allowed to "float" electrically, contact being made with only two outer semiconductor layers.

Fathauer, Robert W.↗
NASA NTRS1989

Photovoltaic-Driven Multiple-Quantum-Well Modulator

Proposed high-performance spatial light modulator consists of multiple-quantum-well, strain-layer superlattice similar to one described in accompanying article, "Strain-Layer-Superlattice Light Modulator" (NPO-16915). Device differs from other one, operates in transmission rather than in resonant reflection and therefore includes only one stack of GaAs/InAs layers having total thickness less than penetration depth (1 to 2 micrometer) of optical modulating signal. Alternating, semitransparent semiconductor layers contain space-charge barriers forming quantum wells. Modulating light (with photon energy greater than semiconductor band gap) induces photovoltaic action, which affects transmission of modulated light (having photon energy less than band gap).

Maserjian, Joseph↗
NASA NTRS1995

Resonant Tunneling Analog-To-Digital Converter

As sampling rates continue to increase, current analog-to-digital converter (ADC) device technologies will soon reach a practical resolution limit. This limit will most profoundly effect satellite and military systems used, for example, for electronic countermeasures, electronic and signal intelligence, and phased array radar. New device and circuit concepts will be essential for continued progress. We describe a novel, folded architecture ADC which could enable a technological discontinuity in ADC performance. The converter technology is based on the integration of multiple resonant tunneling diodes (RTD) and hetero-junction transistors on an indium phosphide substrate. The RTD consists of a layered semiconductor hetero-structure AlAs/InGaAs/AlAs(2/4/2 nm) clad on either side by heavily doped InGaAs contact layers. Compact quantizers based around the RTD offer a reduction in the number of components and a reduction in the input capacitance Because the component count and capacitance scale with the number of bits N, rather than by 2 (exp n) as in the flash ADC, speed can be significantly increased, A 4-bit 2-GSps quantizer circuit is under development to evaluate the performance potential. Circuit designs for ADC conversion with a resolution of 6-bits at 25GSps may be enabled by the resonant tunneling approach.

Broekaert, T. P. E.↗
NASA NTRS1961

The Influence of Surface Coatings on Exo-Electron Emission During Fatigue

A survey of exo-electron emission literature has shown that the mechanism of exo-emission phenomena has yet to be ascertained. Also, there is probably no unique mechanism that will apply to all the exo-emission observations reported. For exo-emission to occur, trapping centers must first be formed to store electrons. Once such centers are formed, they can be made to give up their trapped electrons by the stimulation of light or oxygen. Future investigations will employ light-transparent films for collecting exo-electrons. Also, a carefully controlled experiment is necessary to detect the emission of exo-electrons from the surface of fatiguing metals. Investigations will include high-vacuum fatigue tests, autoradiography, and solid state collector experiments, and will provide a basis for future research on semiconductor layer collection.

COATING↗