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The interdependency of nodes and multicomputer interconnection networks is examined using simple calculations based on the asymptotic properties of queueing networks. Methods are described for choosing interconnection networks that fit individual classes of applications. It is also shown how analytic models can be extended to benchmark existing interconnection networks.
The intent of the proposed effort is the examination of the impact of the elements of parallel architectures on the performance realized in a parallel computation. To this end, three major projects are developed: a language for the expression of high level parallelism, a statistical technique for the synthesis of multicomputer interconnection networks based upon performance prediction, and a queueing model for the analysis of shared memory hierarchies.
We describe decentralized reconfigurable implementation of a conference management system based on the low-level Internet Protocol (IP) multicasting protocol. IP multicasting allows low-cost, world-wide, two-way transmission of data between large numbers of conferencing participants through the Multicasting Backbone (MBone). Each conference is structured as a software bus -- a messaging system that provides a run-time interconnection model that acts as a separate agent (i.e., the bus) for routing, queuing, and delivering messages between distributed programs. Unlike the client-server interconnection model, the software bus model provides a level of indirection that enhances the flexibility and reconfigurability of a distributed system. Current software bus implementations like POLYLITH, however, rely on a centralized bus process and point-to-point protocols (i.e., TCP/IP) to route, queue, and deliver messages. We implement a software bus called the MULTIBUS that relies on a separate process only for routing and uses a reliable IP multicasting protocol for delivery of messages. The use of multicasting means that interconnections are independent of IP machine addresses. This approach allows reconfiguration of bus participants during system execution without notifying other participants of new IP addresses. The use of IP multicasting also permits an economy of scale in the number of participants. We describe the MULITIBUS protocol elements and show how our implementation performs better than centralized bus implementations.
This project involves innovating the way the Quality Assurance organization at the Jet Propulsion Laboratory (JPL) tracks the receiving inspection of JPL Critical Items (JCI) procured from suppliers. The Quality Assurance organization uses a Microsoft Access based front-end to enter items into an inspection queue. The current design has grown to be much more than was expected when the inspection queue system was created in 2007. The goal is to migrate to a web based solution that will allow the handling of more data, multiple input interfaces, and customizable display options. This has been achieved by implementing a divided tables scheme, the use of ColdFusion programming language, and the usage of Web 2.0 technologies such as AJAX and jQuery. These updates will allow for future expansion as well as the standardization of inspection queues for the Quality Assurance organization. When engineers and scientists order flight hardware, they cannot use it straight away. After a spacecraft or a satellite has been launched, it will be impossible to repair; therefore, the parts used must be inspected to make sure they are operating correctly and within the required specifications. The task of inspecting these JPL Critical Items (JCI) falls on the Quality Assurance organization. One of the tools the receiving inspection group uses is a database to maintain a queue of inspections that need to be done and of inspections that have been completed. The current Access interface has worked well but increased amounts of data, multiple input interfaces, and changes to how data is handled have made it necessary to seek a new way of organizing items for inspection. In addition, the different inspection groups have recently been merged and each has different ways of keeping track of inspection information. The ultimate goal is for the new group to have one shared inspection queue and website. To achieve this goal, I have been working with Ian Luczon of Procurement Quality Assurance and 3 Myers Hawkins, another intern, to not only create the new queue for receiving inspection but also a central web portal for the newly combined inspection group.
Cray response to HPCS initiative. Model future petaflop computer interconnect. Parallel discrete event simulation techniques for large scale network simulation. Built on WarpIV engine. Run on laptop and Altix 3000. Can be sized up to 1000 simulated nodes per host node. Good parallel scaling characteristics. Flexible: multiple injectors, arbitration strategies, queue iterators, network topologies.
Several buffer structures are discussed and compared in terms of implementation complexity, interswitch handshaking requirements, and their ability to deal with variations in traffic patterns and message lengths. A new design of buffers is presented that provide non-FIFO message handling and efficient storage allocation for variable size packets using linked lists managed by a simple on-chip controller. The new buffer design is evaluated by comparing it to several alternative designs in the context of a multistage interconnection network. The present modeling and simulations show that the new buffer outperforms alternative buffers and can thus be used to improve the performance of a wide variety of systems currently using less efficient buffers.
The simulation of the network control center (NCC) is in the second phase of development. This phase seeks to further develop the work performed in phase one. Phase one concentrated on the computer systems and interconnecting network. The focus of phase two will be the implementation of the network message dialogues and the resources controlled by the NCC. These resources are requested, initiated, monitored and analyzed via network messages. In the NCC network messages are presented in the form of packets that are routed across the network. These packets are generated, encoded, decoded and processed by the network host processors that generate and service the message traffic on the network that connects these hosts. As a result, the message traffic is used to characterize the work done by the NCC and the connected network. Phase one of the model development represented the NCC as a network of bi-directional single server queues and message generating sources. The generators represented the external segment processors. The served based queues represented the host processors. The NCC model consists of the internal and external processors which generate message traffic on the network that links these hosts. To fully realize the objective of phase two it is necessary to identify and model the processes in each internal processor. These processes live in the operating system of the internal host computers and handle tasks such as high speed message exchanging, ISN and NFE interface, event monitoring, network monitoring, and message logging. Inter process communication is achieved through the operating system facilities. The overall performance of the host is determined by its ability to service messages generated by both internal and external processors.
In general terms, this project aimed at the analysis and design of techniques for very high-speed networking. The formal objectives of the project were to: (1) Identify switch and network technologies for wide-area networks that interconnect a large number of users and can provide individual data paths at gigabit/s rates; (2) Quantitatively evaluate and compare existing and proposed architectures and protocols, identify their strength and growth potentials, and ascertain the compatibility of competing technologies; and (3) Propose new approaches to existing architectures and protocols, and identify opportunities for research to overcome deficiencies and enhance performance. The project was organized into two parts: 1. The design, analysis, and specification of techniques and protocols for very-high-speed network environments. In this part, SRI has focused on several key high-speed networking areas, including Forward Error Control (FEC) for high-speed networks in which data distortion is the result of packet loss, and the distribution of broadband, real-time traffic in multiple user sessions. 2. Congestion Avoidance Testbed Experiment (CATE). This part of the project was done within the framework of the DARTnet experimental T1 national network. The aim of the work was to advance the state of the art in benchmarking DARTnet's performance and traffic control by developing support tools for network experimentation, by designing benchmarks that allow various algorithms to be meaningfully compared, and by investigating new queueing techniques that better satisfy the needs of best-effort and reserved-resource traffic. This document is the final technical report describing the results obtained by SRI under this project. The report consists of three volumes: Volume 1 contains a technical description of the network techniques developed by SRI in the areas of FEC and multicast of real-time traffic. Volume 2 describes the work performed under CATE. Volume 3 contains the source code of all software developed under CATE.