Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “heterogeneous integration (HI)”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

5 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

SIREN: Scaling Ion-Traps by REquiring iNnovative Heterogenous Integration

The SIREN (Scaling Ion Traps by Requiring iNnovative heterogenous integration) project explores the feasibility of heterogeneous integration (HI) as a transformative approach to scaling ion traps, a critical technology for advancing quantum computers and atomic clocks. Traditional ion trap architectures face significant challenges in scalability due to limitations in optical access, fabrication techniques, and material constraints. SIREN addresses these challenges by leveraging HI, which combines different materials and fabrication processes to create more complex and efficient ion trap structures. HI integrated structures can be manufactured without compromising the process to maintain compatibility to ion traps. This project focuses on integrating a separately fabricated waveguide with a fully functional ion trap. The respective alignment between the pieces needs to be accurate to less than 2 µm to ensure that the light from the waveguide can overlap with the trapping region. The fine alignment must also be maintained through an ultra-high vacuum bake, a critical step in preparing an ion trap experiment. The project's outcomes suggest that heterogeneous integration is a promising pathway for overcoming current scalability barriers, paving the way for the next generation of quantum technologies. SIREN's findings contribute significantly to the field, offering a scalable solution that could accelerate the development of practical quantum computers and highly accurate atomic clocks.

42 ENGINEERING↗
DOE OSTI2026

The Heterogeneous Integration of Electronic Components

Heterogeneous integration (HI) of electronics components is broadly recognized as a powerful and crucial enabler for the continued growth of computing and communication. From 2010 onwards, the value of HI is increasingly visible in the advanced packaging used in artificial intelligence, high-performance computing, smartphones and communications product implementations. In this Perspective, we argue that HI is crucial to semiconductors and more broadly to the continued evolution of computing and communications. We use leading-edge advanced packaging examples to represent the value, advancements and opportunities for HI. To succeed, it is critical to develop comprehensive HI roadmaps that inform collaborations across the design, manufacturing and reliability spectrum between systems architects, packaging and semiconductor technologists to common goals. Although this article does not provide a full roadmap, we instead detail additional parameters for artificial intelligence, smartphone and other cellular communication devices, and their constituent building blocks including interconnects, power electronics, photonics, thermal management, reliability, modelling and co-design, to foster greater collaboration opportunities among academia, research laboratories and industry.

42 ENGINEERING↗
DOE OSTI2025

Ion Traps and Packaging for Heterogenous Integration - Chimera

Microfabricated surface ion traps and silicon-based photonics are critical technologies for scaling quantum systems. Current ion trap architectures face scalability and integration challenges due to limitations in optical access, fabrication techniques, and material compatibility. State-of-the-art quantum computers and atomic clocks are investigating monolithic integration, which necessitates custom traps for each ion species and has not overcome the integration hurdles presented by merging these technologies. The Chimera (Ion Traps and Packaging for Heterogeneous Integration) project proposes a novel approach utilizing heterogeneous integration (HI) of ion traps and photonic circuits. This separation of components allows for flexibility in ion trap design and reduces fabrication compromises. The Chimera project specifically designed an ion trap to interface vertically with a separately fabricated waveguide chip and demonstrates the first steps to integrating them at the packaging level. The ion trap features a large area of removed silicon, allowing the photonics chip outputs closer to the ion trap, improving alignment and packaging processes. The alignment must be accurate to < 1 µm to ensure that the light from the waveguide can overlap with the trapping region. This fine alignment must also be maintained through an ultra-high vacuum bake, a critical step in preparing an ion trap experiment. By combining separate chips, we demonstrate a new path for scaling trapped ion technology that is less reliant on monolithic integration. We successfully fabricated a trap with a large area of oxide removed, resulting in a region thinned to about 40 µm, a key milestone toward successful integration.

42 ENGINEERING↗
DOE OSTI2025

Material Needs and Measurement Challenges for Advanced Semiconductor Packaging: Understanding the Soft Side of Science

This Perspective builds upon insights from the National Institute of Standards and Technology (NIST)-organized workshop, “Materials and Metrology Needs for Advanced Semiconductor Packaging Strategies,” held at the 35th annual Electronics Packaging Symposium in Binghamton, NY, on September 5, 2024. It outlines critical challenges and opportunities related to polymer-based “soft” materials in advanced semiconductor packaging, with emphasis on polymer science, measurement science (metrology), and the strategic development of Research-Grade Test Materials (RGTMs). These efforts, led by the NIST CHIPS team, aim to advance the fundamental understanding of structure-property-processing relationships, promote standardized guidelines and innovative methods for material characterization, and accelerate the development, qualification, and adoption of next-generation packaging materials. The Perspective also distills key insights from the panel discussion with industry experts, emphasizing the need for close collaboration among materials scientists, process engineers, and metrology experts to enable a holistic strategy, further highlighting the importance of cross-sector partnerships among industry, academia, and government to address pressing challenges in packaging materials and processes.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Characterization of Fine-Pitch Interconnects for Long-Lifetime HI Applications

This conference talk discusses optimizing gold-gold and gold-ENIG fine-pitch interconnections for Heterogeneous Integration applications, with a focus on longevity. We first look at electrical data from gold-gold bumps subjected to highly accelerated lifetime testing. Then, we discuss using chemical and physical data as a predictor for ENIG bump flip-chip success.

Humphrey, Nicholas James [Sandia National Laborato↗