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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2000

Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100 nm MOSFET's with Ultrathin Gate Oxide

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFET's with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3-D) "atomistic" simulation technique described else-where. MOSFET's with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled-in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide-thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect or the polysilicon grain boundaries on the threshold voltage variation are also presented.

Asenov, Asen↗
NASA NTRS1976

Gate assisted turn-off thyristor with cathode shunts and dynamic gate

A 1,000-V, 200-A gate-assisted turn-off thyristor (GATT) is described, whose design features include an interdigitated shunted cathode, a dynamic gate, a means for optimizing the carrier lifetime level, and a bypass diode. The device physics of gate-assisted turn-off are reviewed. Based on this, improvements in the design are described. It is shown that a prime failure mode can be eliminated and that the gate-assist signal voltage can be substantially decreased by employing a shunted cathode emitter. The test data show excellent turn-on characteristics due to the dynamic gate and the long perimeter of the edge of the main cathode. Turn-off times as short as 3 microsec are obtained. The combination of controlling the carrier lifetime with a precisely controlled and easily variable irradiation dose of high energy electrons with gate assist current provides for simple, precision tailoring of the device characteristics to the intended application.

Schlegel, E. S.↗
NASA NTRS2000

Influence of the Polysilicon Gate on the Random Dopant Induced Threshold Voltage Fluctuations in Sub 100 nm MOSFETS with Thin Gate Oxides

In this paper for the first time we study the influence of the polysilicon gate on the random dopant induced threshold voltage fluctuations in sub 100 nm MOSFETs with tunnelling gate oxides. This is done by using an efficient 3D 'atomistic' simulation technique described elsewhere. Devices with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveale that the polysilicon gate is responsible for a substantial fraction of the threshold voltage fluctuations in both devices when the gate oxide is scaled to tunnelling thickness in the range of 1 - 2 nm.

Asenov, Asen↗
NASA NTRS2016

NextGen Far-Term Concept Exploration for Integrated Gate-to-Gate Trajectory-Based Operations

NASA is currently conducting concept exploration studies toward the definition of a far-term, gate-to-gate concept for Trajectory-Based Operations. This paper presents a basic architectural framework for the far-term concept and discusses some observations about implementation of trajectory-based operations in the National Airspace System. Within the concept, operators and service providers collaboratively negotiate aircraft trajectories, providing agile, optimized, aircraft-specific routing to meet service provider gate-to-gate flow-management constraints and increasing capacity by smoothly and effectively combining flight-deck-based and ground-based metering, merging, and spacing in a mixed-equipage environment. The far-term TBO concept is intended to influence the direction of mid-term TBO research and to inform the definition of stable requirements and standards for TBO communications infrastructure and user equipage.

Johnson, Sally C.↗
NASA NTRS1972

Gate protective device for insulated gate field-effect transistors

Device, which protects insulated gate field-effect transistors, improves reliability through utilization of layers of conductive material on top of each alternating semiconductor material region. Separation of layers is necessary to prevent shorting out junctions between alternating regions.

Sunshine, R. A.↗
NASA NTRS1994

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Sewell, James S.↗
NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗
NASA NTRS2016

An Integrated Gate Turnaround Management Concept Leveraging Big Data Analytics for NAS Performance Improvements

"Gate Turnaround" plays a key role in the National Air Space (NAS) gate-to-gate performance by receiving aircraft when they reach their destination airport, and delivering aircraft into the NAS upon departing from the gate and subsequent takeoff. The time spent at the gate in meeting the planned departure time is influenced by many factors and often with considerable uncertainties. Uncertainties such as weather, early or late arrivals, disembarking and boarding passengers, unloading/reloading cargo, aircraft logistics/maintenance services and ground handling, traffic in ramp and movement areas for taxi-in and taxi-out, and departure queue management for takeoff are likely encountered on the daily basis. The Integrated Gate Turnaround Management (IGTM) concept is leveraging relevant historical data to support optimization of the gate operations, which include arrival, at the gate, departure based on constraints (e.g., available gates at the arrival, ground crew and equipment for the gate turnaround, and over capacity demand upon departure), and collaborative decision-making. The IGTM concept provides effective information services and decision tools to the stakeholders, such as airline dispatchers, gate agents, airport operators, ramp controllers, and air traffic control (ATC) traffic managers and ground controllers to mitigate uncertainties arising from both nominal and off-nominal airport gate operations. IGTM will provide NAS stakeholders customized decision making tools through a User Interface (UI) by leveraging historical data (Big Data), net-enabled Air Traffic Management (ATM) live data, and analytics according to dependencies among NAS parameters for the stakeholders to manage and optimize the NAS performance in the gate turnaround domain. The application will give stakeholders predictable results based on the past and current NAS performance according to selected decision trees through the UI. The predictable results are generated based on analysis of the unique airport attributes (e.g., runway, taxiway, terminal, and gate configurations and tenants), and combined statistics from past data and live data based on a specific set of ATM concept-of-operations (ConOps) and operational parameters via systems analysis using an analytic network learning model. The IGTM tool will then bound the uncertainties that arise from nominal and off-nominal operational conditions with direct assessment of the gate turnaround status and the impact of a certain operational decision on the NAS performance, and provide a set of recommended actions to optimize the NAS performance by allowing stakeholders to take mitigation actions to reduce uncertainty and time deviation of planned operational events. An IGTM prototype was developed at NASA Ames Simulation Laboratories (SimLabs) to demonstrate the benefits and applicability of the concept. A data network, using the System Wide Information Management (SWIM)-like messaging application using the ActiveMQ message service, was connected to the simulated data warehouse, scheduled flight plans, a fast-time airport simulator, and a graphic UI. A fast-time simulation was integrated with the data warehouse or Big Data/Analytics (BAI), scheduled flight plans from Aeronautical Operational Control AOC, IGTM Controller, and a UI via a SWIM-like data messaging network using the ActiveMQ message service, illustrated in Figure 1, to demonstrate selected use-cases showing the benefits of the IGTM concept on the NAS performance.

Efficent ATM systems↗
NASA NTRS2005

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

MacLeod, Todd C.↗
NASA NTRS1999

Computer Simulation Studies of Ion Channel Gating: Characteristics of the M2 Channel of Influenza-A Virus in a Phospholipid Bilayer

The 25 amino acids long, transmembrane fragment of the Influenza virus M2 protein forms a homotetrameric channel that transports protons across lipid bilayers. It has been postulated that high efficiency and selectivity of this process is due to gating by four histidine residues that occlude the channel lumen in the closed state. Two mechanisms of gating have been postulated. In one mechanism, the proton is "shuttled" through the gate by attaching to the delta nitrogen atom on the extracellular side of the imidazole ring, followed by the release of the proton attached to the epsilon nitrogen atom on the opposite side. In the second mechanism, the four histidines move away from each other due to electrostatic repulsion upon protonation, thus opening the gate sufficiently that a wire of water molecules can penetrate the gate. Then, protons are transported by "hopping" along the wire. In this paper, both mechanisms are evaluated in a series of molecular dynamics simulations by investigating stability of different protonation states of the channel that are involved in these mechanisms. For the shuttle mechanism, these are states with all epsilon protonated histidines, one biprotonated residue or one histidine protonated in the delta position. For the gate opening mechanism, this is the state in which all four histidines are biprotonated. In addition, a state with two biprotonated histidines is considered. For each system, composed of the protein channel embedded in phospholipid bilayer located between two water lamellae, a molecular dynamics trajectory of approximately 1.3 ns (after equilibration) was obtained. It is found that the states involved in the shuttle mechanism are stable during the simulations. Furthermore, the orientations and dynamics of water molecules near the gate are conducive to proton transfers involved in the shuttle. In contract, the fully biprotonated state, implicated in the gate opening mechanism, is not stable and the channel looses its structural integrity. If only two histidines are biprotonated the channel deforms but remains intact with the gate mostly closed. In summary, the results of this study lend support to the shuttle mechanism but not to the gate opening mechanism of proton gating in M2.

Schweighofer, Karl J.↗
NASA NTRS1989

Monolithic transistor gate energy recovery system

Energy is recovered from an insulated gate semiconductor switch, such as a MOSFET, that is otherwise lost in the gate capacitance by producing a notch in the gate control voltage for an interval B following an interval A after initial application of a gate control voltage pulse for turning the switch on, and a notch for an interval C following termination of the gate control voltage pulse followed by interval D during which the switch is turned on again, where each interval is a period .DELTA.T given by ##EQU1## L.sub.s is the inductance (discrete and/or parasitic) in series with the gate electrode of the insulated gate semiconductor switch, and C.sub.in is the capacitance of that switch between its gate and source electrodes. The interval .DELTA.T may be provided directly by timing in a pulse forming circuit for the gate control voltage applied, or adaptively by sensing the gate voltage v.sub.g and comparing it with fixed progressively higher voltages v.sub.1, v.sub.2 and v.sub.3, where v.sub.2 is intermediate v.sub.1 and v.sub.3 which correspond to the lower and upper levels of v.sub.g as the switch is turned off and on.

Rippel, Wally E.↗
NASA NTRS2011

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Krasowski, Michael J.↗
NASA NTRS2000

Computer simulation of ion channel gating: the M(2) channel of influenza A virus in a lipid bilayer

The transmembrane fragment of the influenza virus M(2) protein forms a homotetrameric channel that transports protons. In this paper, we use molecular dynamics simulations to help elucidate the mechanism of channel gating by four histidines that occlude the channel lumen in the closed state. We test two competing hypotheses. In the "shuttle" mechanism, the delta nitrogen atom on the extracellular side of one histidine is protonated by the incoming proton, and, subsequently, the proton on the epsilon nitrogen atom is released on the opposite side. In the "water-wire" mechanism, the gate opens because of electrostatic repulsion between four simultaneously biprotonated histidines. This allows for proton transport along the water wire that penetrates the gate. For each system, composed of the channel embedded in a hydrated phospholipid bilayer, a 1.3-ns trajectory was obtained. It is found that the states involved in the shuttle mechanism, which contain either single-protonated histidines or a mixture of single-protonated histidines plus one biprotonated residue, are stable during the simulations. Furthermore, the orientations and dynamics of water molecules near the gate are conducive to proton transfer. In contrast, the fully biprotonated state is not stable. Additional simulations show that if only two histidines are biprotonated, the channel deforms but the gate remains closed. These results support the shuttle mechanism but not the gate-opening mechanism of proton gating in M(2).

NASA Center ARC↗
NASA NTRS1977

DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

Gosney, W. M.↗
NASA NTRS1989

Gallium arsenide processing for gate array logic

The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

Cole, Eric D.↗
NASA NTRS2003

Looking for Speed!! Go Optical Ultra-Fast Photonic Logic Gates for the Future Optical Communication and Computing

Recently, we developed two ultra-fast all-optical switches in the nanosecond and picosecond regimes. The picosecond switch is made of a polydiacetylene thin film coated on the interior wall of a hollow capillary of approximately 50 micron diameter by a photo-polymerization process. In the setup a picosecond Nd:YAG laser at 10 Hz and at 532 nm with a pulse duration of approximately 40 ps was sent collinearly along a cw He-Ne laser beam and both were waveguided through the hollow capillary. The setup functioned as an Exclusive OR gate. On the other hand, the material used in the nanosecond switch is a phthalocyanine thin film, deposited on a glass substrate by a vapor deposition technique. In the setup a nanosecond, 10 Hz, Nd:YAG laser of 8 ns pulse duration was sent collinearly along a cw He-Ne laser beam and both were wave-guided through the phthalocyanine thin film. The setup in this case functioned as an all-optical AND logic gate. The characteristic table of the ExOR gate in polydiacetylene film was attributed to an excited state absorption process, while that of the AND gate was attributed to a saturation process of the first excited state. Both mechanisms were thoroughly investigated theoretically and found to agree remarkably well with the experimental results. An all-optical inverter gate has been designed but has not yet been demonstrated. The combination of all these three gates form the foundation for building all the necessary gates needed to build a prototype of an all-optical system.

Abdeldayem, Hossin↗
NASA NTRS1972

Shielded silicon gate complementary MOS integrated circuit.

An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

Lin, H. C.↗