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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRSDate not supplied

Advancing Metasurfaces Towards New Frontiers: Nonvolatile Reconfigurable Optics

The applications of adaptive optics extend across multiple sectors, encompassing areas such as LiDAR, biological and chemical sensing, and free-space communications. In this study, we report on the design, fabrication, testing, and modeling of electrically reconfigurable metasurfaces using a low-loss high contrast phase change material, Ge2Sb2Se4Te integrated with an IR-transparent silicon microheater. Through this work, we introduce a reliable architecture for switching PCM-based metasurfaces within an integrated circuit configuration which is compatible with standard foundry fabrication processes. We demonstrate the capability of controlling the transmission of electromagnetic waves through the precise stimulation of PCM-based pixels, each spanning a few hundred microns, over numerous cycles. By leveraging PCM-based pixels, we unlock the potential to create metasurfaces encompassing a diverse range of functionalities such as dielectric filters, metalens, or beam steering devices, which is governed by the design of the meta-atoms. Further, we perform an in-depth investigation into the failure mechanism utilizing techniques such as Fourier transform IR spectroscopy (FTIR), transmission electron microscopy (TEM), energy dispersive spectroscopy (EDS), and thermal modeling. According to our results, due to a sharp temperature rise at the PCM/heater interface, we observe severe delamination of the PCM from the heater. More uniform PCM deposition, better adhesion at the PCM/heater interface, and a more uniform temperature distribution in the device could potentially mitigate the failure and lead to a longer life-time. By addressing these challenges, we aim to unlock the full potential of PCM-based devices and advance the field of adaptive optics.

Phase change material↗
NASA NTRSDate not supplied

Toward High-Endurance Nonvolatile Reconfigurable Metasurfaces

The applications of adaptive optics extend across multiple sectors, encompassing areas such as LiDAR, biological and chemical sensing, and free-space optical communications. The advent of metasurfaces optics with reconfigurability has offered a versatile platform for the design of compact optical components, offering a compelling alternative to their conventional bulky counterparts. In this study, we introduce the PROWESS (Phase change Reconfigurable Optical WavEfront Synthesis System project at NASA LaRC), electrically reconfigurable metasurfaces using low-loss, high-contrast phase change material (PCM), Ge2Sb2Se4Te integrated with IR-transparent silicon microheater for various practical applications. The talk covers a reliable platform for switching large-scale PCM-based devices utilizing a microheater and an architecture for the metasurface switching within an integrated circuit configuration, which is compatible with standard foundry fabrication processes. The utilization of near- to midinfrared transparent silicon microheater in the proposed architecture opens possibilities for the development of reconfigurable transmissive optics such as filters, zoom lenses, and beam steering modules. We demonstrated switching of 140 µm × 140 µm PCM pixel, on a 200 µm × 200 µm silicon microheater for several thousand cycles. Further, we performed an in-depth investigation into the failure mechanism utilizing techniques such as transmission electron microscopy and thermal modeling. Guidelines for device performance improvement are proposed, and an improved design with larger endurance is shown in progress. With further progress, we aim to unlock the full potential of PCM-based devices and advance the field of adaptive optics with demonstrable examples including a reconfigurable beam steerer for ocean surface flash LiDAR and Navigation Doppler LiDAR for precise lunar landing missions.

metasurface optics↗
NASA NTRSDate not supplied

Phase-change Reconfigurable Optical WavEfront Synthesis System (PROWESS)

We report the design, fabrication, and testing of electrically tunable metasurface k-space filters based on the low-loss, high-contrast phase-change material GSST and a transparent Si electrode heating architecture. A 10x10 array of PCM elements integrated with Si heaters was fabricated via foundry processes, and used to actively control the crystallinity of a metasurface consisting of GSST nano antennae. By selectively varying the structural state of individual PCM elements, specific k-vectors of transmitted light can effectively be filtered out, resulting in improved imaging quality by reducing the scattered light that reaches a detector. Optimized doping profiles in the Si heaters allow for uniform, low power, reliable and repeatable switching of the GSST state. Compared to other k-space filters, this new architecture is completely transparent to the wavelength of interest and can be actively reconfigured in real time with high performance, low power consumption and a small footprint. The 10x10 array device is a proof-of-concept demonstration that can enable high-resolution arbitrary wavefront synthesis and correction in the future, with key applications in optical communications, beam steering, remote sensing, and adaptive optics.

phase change material↗
NASA NTRS1990

Using advanced microelectronic test chips to qualify ASIC's for space

Qualification procedures for complex integrated circuits are being developed under a U.S. government program known as Qualified Manufacturing Lines (QML). This effort is focused on circuits designed by IC manufacturers and has not addressed application specific IC's (ASIC's) designed at system houses. The qualification procedures described here are intended to be responsive to the needs of system houses who design their own ASIC's and have them fabricated at Silicon foundries. A particular focus of this presentation will be the use of the TID (total Ionizing Dose) Chip to evaluate CMOS foundry processes and to provide parameters for circuit simulators. This chip is under development as a standard chip for qualifying the total dose aspects of ASIC's. The benefits of standardization are that the results will be well understood and easy to interpret. Data is presented and compared for 1.6 micron and 3.0 micron CMOS. The data shows that 1.6 micron CMOS is significantly harder than 3.0 micron CMOS. Two failure modes are explored: (1) the radiation-induced degradation of timing delays; and (2) radiation-induced leakage currents.

Buehler, M. G.↗
NASA NTRS2003

Superalloy Lattice Block Developed for Use in Lightweight, High-Temperature Structures

Successful development of advanced gas turbine engines for aircraft will require lightweight, high-temperature components. Currently titanium-aluminum- (TiAl) based alloys are envisioned for such applications because of their lower density (~4 g/cm3) in comparison to superalloys (~8.5 g/cm3), which have been utilized for hot turbine engine parts for over 50 years. However, a recently developed concept (lattice block) by JAMCORP, Inc., of Willmington, Massachusetts, would allow lightweight, high-temperature structures to be directly fabricated from superalloys and, thus, take advantage of their well-known, characterized properties. In its simplest state, lattice block is composed of thin ligaments arranged in a three dimensional triangulated trusslike configuration that forms a structurally rigid panel. Because lattice block can be fabricated by casting, correctly sized hardware is produced with little or no machining; thus very low cost manufacturing is possible. Together, the NASA Glenn Research Center and JAMCORP have extended their lattice block methodology for lower melting materials, such as Al alloys, to demonstrate that investment casting of superalloy lattice block is possible. This effort required advances in lattice block pattern design and assembly, higher temperature mold materials and mold fabrication technology, and foundry practice suitable for superalloys (ref. 1). Lattice block panels have been cast from two different Ni-base superalloys: IN 718, which is the most commonly utilized superalloy and retains its strength up to 650 C; and MAR M247, which possesses excellent mechanical properties to at least 1100 C. In addition to the open-cell lattice block geometry, same-sized lattice block panels containing a thin (~1-mm-thick) solid face on one side have also been cast from both superalloys. The elevated-temperature mechanical properties of the open cell and face-sheeted superalloy lattice block panels are currently being examined, and the microstructure is being characterized in terms of casting defects. In addition, a small study (ref. 3) is being undertaken with GE Aircraft Engines to determine the suitability of superalloy lattice block for engine components.

Hebsur, Mohan G.↗
NASA NTRS1988

A CMOS matrix for extracting MOSFET parameters before and after irradiation

An addressable matrix of 16 n- and 16 p-MOSFETs was designed to extract the dc MOSFET parameters for all dc gate bias conditions before and after irradiation. The matrix contains four sets of MOSFETs, each with four different geometries that can be biased independently. Thus the worst-case bias scenarios can be determined. The MOSFET matrix was fabricated at a silicon foundry using a radiation-soft CMOS p-well LOCOS process. Co-60 irradiation results for the n-MOSFETs showed a threshold-voltage shift of -3 mV/krad(Si), whereas the p-MOSFETs showed a shift of 21 mV/krad(Si). The worst-case threshold-voltage shift occurred for the n-MOSFETs, with a gate bias of 5 V during the anneal. For the p-MOSFETs, biasing did not affect the shift in the threshold voltage. A parasitic MOSFET dominated the leakage of the n-MOSFET biased with 5 V on the gate during irradiation. Co-60 test results for other parameters are also presented.

Blaes, B. R.↗
NASA NTRS1997

A Low Cost Rad-Tolerant Standard Cell Library

This paper describes circuit design techniques developed at the NASA Institute of Advanced Microelectronics that have been shown to protect CMOS circuits from the deleterious effects of the natural space radiation environment. The IAuE is leading a program to incorporate these radiation-tolerance providing design techniques into a commercial standard cell library that will be used in conjunction with available Electronic Design Automation tools to produce space flight qualified microelectronics fabricated at modern commercial CMOS foundries.

Gambles, Jody W.↗
NASA NTRS1996

Highly Efficient Amplifier for Ka-Band Communications

An amplifier developed under a Small Business Innovation Research (SBIR) contract will have applications for both satellite and terrestrial communications. This power amplifier uses an innovative series bias arrangement of active devices to achieve over 40-percent efficiency at Ka-band frequencies with an output power of 0.66 W. The amplifier is fabricated on a 2.0- by 3.8-square millimeter chip through the use of Monolithic Microwave Integrated Circuit (MMIC) technology, and it uses state-of-the-art, Pseudomorphic High-Electron-Mobility Transistor (PHEMT) devices. Although the performance of the MMIC chip depends on these high-performance devices, the real innovations here are a unique series bias scheme, which results in a high-voltage chip supply, and careful design of the on-chip planar output stage combiner. This design concept has ramifications beyond the chip itself because it opens up the possibility of operation directly from a satellite power bus (usually 28 V) without a dc-dc converter. This will dramatically increase the overall system efficiency. Conventional microwave power amplifier designs utilize many devices all connected in parallel from the bias supply. This results in a low-bias voltage, typically 5 V, and a high bias current. With this configuration, substantial I(sup 2) R losses (current squared times resistance) may arise in the system bias-distribution network. By placing the devices in a series bias configuration, the total current is reduced, leading to reduced distribution losses. Careful design of the on-chip planar output stage power combiner is also important in minimizing losses. Using these concepts, a two-stage amplifier was designed for operation at 33 GHz and fabricated in a standard MMIC foundry process with 0.20-m PHEMT devices. Using a 20-V bias supply, the amplifier achieved efficiencies of over 40 percent with an output power of 0.66 W and a 16-dB gain over a 2-GHz bandwidth centered at 33 GHz. With a 28-V bias, a power level of 1.1 W was achieved with a 12-dB gain and a 36-percent efficiency. This represents the best reported combination of power and efficiency at this frequency. In addition to delivering excellent power and gain, this Ka-band MMIC power amplifier has an efficiency that is 10 percent greater than existing designs. The unique design offers an excellent match for spacecraft applications since the amplifier supply voltage is closely matched to the typical value of spacecraft bus voltage. These amplifiers may be used alone in applications of 1 W or less, or several may be combined or used in an array to produce moderate power, Ka-band transmitters with minimal power combining and less thermal stress owing to the combination of excellent efficiency and power output. The higher voltage operation of this design may also save mass and power because the dc-dc power converter is replaced with a simpler voltage regulator.

Source record↗
NASA NTRS1990

Assessing the SEU resistance of CMOS latches using alpha-particle sensitive test circuits

The importance of Cosmic Rays on the performance of integrated circuits (IC's) in a space environment is evident in the upset rate of the Tracking and Data Relay Satellite (TDRS) launched in Apr. 1983. This satellite experiences a single-event-upset (SEU) per day which must be corrected from the ground. Such experience caused a redesign of the Galileo spacecraft with SEU resistant IC's. The solution to the SEU problem continues to be important as the complexity of spacecraft grows, the feature size of IC's decreases, and as space systems are designed with circuits fabricated at non-radiation hardened foundries. This paper describes an approach for verifying the susceptibility of CMOS latches to heavy-ion induced state changes. The approach utilizes alpha particles to induce the upsets in test circuits. These test circuits are standard cells that have offset voltages which sensitize the circuits to upsets. These results are then used to calculate the upsetability at operating voltages. In this study results are presented for the alpha particle upset of a six-transistor static random access memory (SRAM) cell. Then a methodology is described for the analysis of a standard-cell inverter latch.

Buehler, M.↗
NASA NTRS1994

Monolithic Optical-To-Electronic Receiver

Monolithic optoelectronic integrated circuit converts multiplexed digital optical signals into electrical signals, separates, and distributes them to intended destinations. Developed to deliver phase and amplitude commands to monolithic microwave integrated circuits (MMIC's) at elements of millimeter-wave phased-array antenna from single optical fiber driven by external array controller. Also used in distribution of high-data-rate optical communications in local-area networks (LAN's). Notable features include options for optical or electrical clock inputs; outputs for raw data, addresses, and instructions for diagnosis; and optical-signal-detection circuit used to reduce power consumption by 80 percent between data-transmission times. Chip fabricated by processes available at many major semiconductor foundries. Distribution of digital signals in aircraft, automobiles, and ships potential application.

Kunath, Richard↗
NASA NTRS1993

NASA Space Engineering Research Center for VLSI System Design

This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

Source record↗
NASA NTRS2005

Improvements in Fabrication of Sand/Binder Cores for Casting

Three improvements have been devised for the cold-box process, which is a special molding process used to make sand/binder cores for casting hollow metal parts. These improvements are: The use of fiber-reinforced composite binder materials (in contradistinction to the non-fiber-reinforced binders used heretofore), The substitution of a directed-vortex core-blowing subprocess for a prior core-blowing process that involved a movable gassing plate, and The use of filters made from filtration-grade fabrics to prevent clogging of vents. For reasons that exceed the scope of this article, most foundries have adopted the cold-box process for making cores for casting metals. However, this process is not widely known outside the metal-casting industry; therefore, a description of pertinent aspects of the cold-box process is prerequisite to a meaningful description of the aforementioned improvements. In the cold-box process as practiced heretofore, sand is first mixed with a phenolic resin (considered to be part 1 of a three-part binder) and an isocyanate resin (part 2 of the binder). Then by use of compressed air, the mixture is blown into a core box, which is a mold for forming the core. Next, an amine gas (part 3 of the binder) that acts as a catalyst for polymerization of parts 1 and 2 is blown through the core box. Alternatively, a liquid amine that vaporizes during polymerization can be incorporated into the sand/resin mixture. Once polymerization is complete, the amine gas is purged from the core box by use of compressed air. The finished core is then removed from the core box.

Bakhitiyarov, Sayavur I.↗
NASA NTRS2023

Processing Choices for Achieving Long Term IC Operation at 500° C

The prospects for beneficial infusion of integrated circuits (ICs) into previously inaccessible extreme-temperature application environments has increased with recent NASA Glenn demonstrations of 4H-SiC Junction Field Effect Transistor & Resistor (JFET-R) chips functioning for over a year at 500 °C in air ambient [1]. This paper focuses on fabrication process choices believed key to demonstrated 500 °C durability that must be considered when porting this uniquely durable IC capability into commercial foundry manufacturing.

SiC, JFET, Integrated Circuits, High-Temperature, ↗
NASA NTRSDate not supplied

Processing Choices for Achieving Long Term IC Operation at 500 °C

The prospects for beneficial infusion of integrated circuits (ICs) into previously inaccessible extreme-temperature application environments has increased with recent NASA Glenn demonstrations of 4H-SiC Junction Field Effect Transistor & Resistor (JFET-R) chips functioning for over a year at 500 °C in air ambient. This paper focuses on fabrication process choices believed key to demonstrated 500 °C durability that must be considered when porting this uniquely durable IC capability into commercial foundry manufacturing.

silicon carbide↗
NASA NTRS2005

Improved Method of Manufacturing SiC Devices

The phrase, "common-layered architecture for semiconductor silicon carbide" ("CLASSiC") denotes a method of batch fabrication of microelectromechanical and semiconductor devices from bulk silicon carbide. CLASSiC is the latest in a series of related methods developed in recent years in continuing efforts to standardize SiC-fabrication processes. CLASSiC encompasses both institutional and technological innovations that can be exploited separately or in combination to make the manufacture of SiC devices more economical. Examples of such devices are piezoresistive pressure sensors, strain gauges, vibration sensors, and turbulence-intensity sensors for use in harsh environments (e.g., high-temperature, high-pressure, corrosive atmospheres). The institutional innovation is to manufacture devices for different customers (individuals, companies, and/or other entities) simultaneously in the same batch. This innovation is based on utilization of the capability for fabrication, on the same substrate, of multiple SiC devices having different functionalities (see figure). Multiple customers can purchase shares of the area on the same substrate, each customer s share being apportioned according to the customer s production-volume requirement. This makes it possible for multiple customers to share costs in a common foundry, so that the capital equipment cost per customer in the inherently low-volume SiC-product market can be reduced significantly. One of the technological innovations is a five-mask process that is based on an established set of process design rules. The rules provide for standardization of the fabrication process, yet are flexible enough to enable multiple customers to lay out masks for their portions of the SiC substrate to provide for simultaneous batch fabrication of their various devices. In a related prior method, denoted multi-user fabrication in silicon carbide (MUSiC), the fabrication process is based largely on surface micromachining of poly SiC. However, in MUSiC one cannot exploit the superior sensing, thermomechanical, and electrical properties of single-crystal 6H-SiC or 4H-SiC. As a complement to MUSiC, the CLASSiC five-mask process can be utilized to fabricate multiple devices in bulk single-crystal SiC of any polytype. The five-mask process makes fabrication less complex because it eliminates the need for large-area deposition and removal of sacrificial material. Other innovations in CLASSiC pertain to selective etching of indium tin oxide and aluminum in connection with multilayer metallization. One major characteristic of bulk micromachined microelectromechanical devices is the presence of three-dimensional (3D) structures. Any 3D recesses that already exist at a given step in a fabrication process usually make it difficult to apply a planar coat of photoresist for metallization and other subsequent process steps. To overcome this difficulty, the CLASSiC process includes a reversal of part of the conventional flow: Metallization is performed before the recesses are etched.

Okojie, Robert S.↗
NASA NTRS2011

Nanoscale Deformable Optics

Several missions and instruments in the conceptual design phase rely on the technique of interferometry to create detectable fringe patterns. The intimate emplacement of reflective material upon electron device cells based upon chalcogenide material technology permits high-speed, predictable deformation of the reflective surface to a subnanometer or finer resolution with a very high degree of accuracy. In this innovation, a layer of reflective material is deposited upon a wafer containing (perhaps in the millions) chalcogenic memory cells with the reflective material becoming the front surface of a mirror and the chalcogenic material becoming a means of selectively deforming the mirror by the application of heat to the chalcogenic material. By doing so, the mirror surface can deform anywhere from nil to nanometers in spots the size of a modern day memory cell, thereby permitting realtime tuning of mirror focus and reflectivity to mitigate aberrations caused elsewhere in the optical system. Modern foundry methods permit the design and manufacture of individual memory cells having an area of or equal to the Feature (F) size of the design (assume 65 nm). Fabrication rules and restraints generally require the instantiation of one memory cell to another no closer than 1.5 F, or, for this innovation, 90 nm from its neighbor in any direction. Chalcogenide is a semiconducting glass compound consisting of a combination of chalcogen ions, the ratios of which vary according to properties desired. It has been shown that the application of heat to cells of chalcogenic material cause a large alteration in resistance to the range of 4 orders of magnitude. It is this effect upon which chalcogenidebased commercial memories rely. Upon removal of the heat source, the chalcogenide rapidly cools and remains frozen in the excited state. It has also been shown that the chalcogenide expands in volume because of the applied heat, meaning that the coefficient of expansion of chalcogenic materials is larger than 1. In this innovation, chalcogenidebased cells are addressed (as though they are a memory), and heated and cooled according to well-established criteria. In doing so, the exact size of chalcogenide cell deformation is known and predictable; therefore, the deformation of the reflective surface is, likewise, known and predictable. Control electronics can also be implemented so that a closed-loop feedback can be maintained. Changing the contents of the chalcogenide memory cells can compensate for any change in environmental effects that might cause a change in optical path. This real-time control provides significant control and stability in use conditions.

Strauss, Karl F.↗
NASA NTRSDate not supplied

Progress Towards SiC ASICs for Extreme Temperature and Radiation Environments

This presentation describes development and demonstrations of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. Silicon carbide (SiC) junction field effect transistor-resistor (JFET-R) ICs fabricated by NASA Glenn Research Center with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient, 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber, and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C temperature span) without significant change in signal (input /output) or power supply voltages. While the operating frequency and functional complexity is far below silicon-based ICs, these SiC application specific ICs (ASICs) are nevertheless becoming capable of providing unique and advantageous harsh-environment circuit functionality without cooling/sheltering overhead. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards manufacture, a majority of processing steps to realize the next SiC JFET-R IC prototype wafer run have been outsourced to commercial foundry. It is expected that further upscaling combined with technology transfer to commercial production will lower investment and risk barriers to useful application deployment.

high temperature↗
NASA NTRS1986

Prototyping and implementing flight qualifiable semicustom CMOS P-well bulk integrated circuits in the JPL environment

Presently, there are many difficulties associated with implementing application specific custom or semi-custom (standard cell based) integrated circuits (ICs) into JPL flight projects. One of the primary difficulties is developing prototype semi-custom integrated circuits for use and evaluation in engineering prototype flight hardware. The prototype semi-custom ICs must be extremely cost-effective and yet still representative of flight qualifiable versions of the design. A second difficulty is encountered in the transport of the design from engineering prototype quality to flight quality. Normally, flight quality integrated circuits have stringent quality standards, must be radiation resistant and should consume minimal power. It is often not necessary or cost effective, however, to impose such stringent quality standards on engineering models developed for systems analysis in controlled lab environments. This article presents work originally initiated for ground based applications that also addresses these two problems. Furthermore, this article suggests a method that has been shown successful in prototyping flight quality semi-custom ICs through the Metal Oxide Semiconductor Implementation Service (MOSIS) program run by the University of Southern California's Information Sciences Institute. The method has been used successfully to design and fabricate through the MOSIS three different semi-custom prototype CMOS p-well chips. The three designs make use of the work presented and were designed consistent with design techniques and structures that are flight qualifiable, allowing one hour transfer of the design from engineering model status to flight qualifiable foundry-ready status through methods outlined in this article.

Olson, E. M.↗