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All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

Ferroelectric Field Effect Transistor Model Using Partitioned Ferroelectric Layer and Partial Polarization

A model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. The model is based on an existing model that incorporates partitioning of the ferroelectric layer to calculate the polarization within the ferroelectric material. The model incorporates several new aspects that are useful to the user. It takes into account the effect of a non-saturating gate voltage only partially polarizing the ferroelectric material based on the existing remnant polarization. The model also incorporates the decay of the remnant polarization based on the time history of the FFET. A gate pulse of a specific voltage; will not put the ferroelectric material into a single amount of polarization for that voltage, but instead vary with previous state of the material and the time since the last change to the gate voltage. The model also utilizes data from FFETs made from different types of ferroelectric materials to allow the user just to input the material being used and not recreate the entire model. The model also allows the user to input the quality of the ferroelectric material being used. The ferroelectric material quality can go from a theoretical perfect material with little loss and no decay to a less than perfect material with remnant losses and decay. This model is designed to be used by people who need to predict the external characteristics of a FFET before the time and expense of design and fabrication. It also allows the parametric evaluation of quality of the ferroelectric film on the overall performance of the transistor.

MacLeod, Todd C.↗
NASA NTRS2006

Ferroelectric Material Application: Modeling Ferroelectric Field Effect Transistor Characteristics from Micro to Nano

All present ferroelectric transistors have been made on the micrometer scale. Existing models of these devices do not take into account effects of nanoscale ferroelectric transistors. Understanding the characteristics of these nanoscale devices is important in developing a strategy for building and using future devices. This paper takes an existing microscale ferroelectric field effect transistor (FFET) model and adds effects that become important at a nanoscale level, including electron velocity saturation and direct tunneling. The new model analyzed FFETs ranging in length from 40,000 nanometers to 4 nanometers and ferroelectric thickness form 200 nanometers to 1 nanometer. The results show that FFETs can operate on the nanoscale but have some undesirable characteristics at very small dimensions.

MacLeod, Todd, C.↗
NASA NTRS1981

Semiconductor-ferroelectric nonvolatile memory using anomalous high photovoltages in ferroelectric ceramics

A small ferroelectric ceramic element is used with an insulating gate transistor and two diodes as an electrically addressed, nonvolatile memory device which is read out nondestructively. The device uses the anomalous photovoltaic effect in ferroelectric ceramics, an effect in which the polarity and magnitude of photovoltages depend on the direction and magnitude of remanent polarization. Experimental results give memory characteristics. The device could be programmed with pulses as short as 200 ns. There is long-time retention of stored data.

Brody, P. S.↗
NASA NTRS2006

Design of a Multi-Level/Analog Ferroelectric Memory Device

Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

MacLeod, Todd C.↗
NASA NTRS2000

Ferroelectric Pump

A ferroelectric pump has one or more variable volume pumping chambers internal to a housing. Each chamber has at least one wall comprising a dome shaped internally prestressed ferroelectric actuator having a curvature and a dome height that varies with an electric voltage applied between an inside and outside surface of the actuator. A pumped medium flows into and out of each pumping chamber in response to displacement of the ferroelectric actuator. The ferroelectric actuator is mounted within each wall and isolates each ferroelectric actuator from the pumped medium, supplies a path for voltage to be applied to each ferroelectric actuator, and provides for positive containment of each ferroelectric actuator while allowing displacement of the entirety of each ferroelectric actuator in response to the applied voltage.

Jalink, Antony, Jr.↗
NASA NTRS2001

Future Development of Dense Ferroelectric Memories for Space Applications

The availability of high density, radiation tolerant, nonvolatile memories is critical for space applications. Ferroelectric memories, when fabricated with radiation hardened complementary metal oxide semiconductors (CMOS), can be manufactured and packaged to provide high density replacements for Flash memory, which is not radiation tolerant. Previous work showed ferroelectric memory cells to be resistant to single event upsets and proton irradiation, and ferroelectric storage capacitors to be resistant to neutron exposure. In addition to radiation hardness, the fast programming times, virtually unlimited endurance, and low voltage, low power operation make ferroelectric memories ideal for space missions. Previously, a commercial double level metal 64-kilobit ferroelectric memory was presented. Although the capabilities of radiation hardened wafer fabrication facilities lag behind those of the most modern commercial wafer fabrication facilities, several paths to achieving radiation tolerant, dense ferroelectric memories are emerging. Both short and long term solutions are presented in this paper. Although worldwide major semiconductor companies are introducing commercial ferroelectric memories, funding limitations must be overcome to proceed with the development of high density, radiation tolerant ferroelectric memories.

Philpy, Stephen C.↗
NASA NTRS2007

Performance Measurement of a Multi-Level/Analog Ferroelectric Memory Device Design

Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determinethe amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

MacLeod, Todd C.↗
NASA NTRS2003

Performance Enhancement of Tunable Bandpass Filters Using Selective Etched Ferroelectric Thin Films

The inclusion of voltage-tunable barium strontium titanate (BSTO) thin films into planar band pass filters offers tremendous potential to increase their versatility. The ability to tune the passband so as to correct for minor deviations in manufacturing tolerances, or to completely reconfigure the operating frequencies of a microwave communication system, are highly sought-after goals. However, use of ferroelectric films in these devices results in higher dielectric losses, which in turn increase the insertion loss and decrease the quality factors of the filters. This study explores the use of patterned ferroelectric layers to minimize dielectric losses without degrading tunability. Patterning the ferroelectric layers enables us to constrict the width of the ferroelectric layers between the coupled microstrip lines, and minimize losses due to ferroelectric layers. Coupled one-pole microstrip bandpass filters with fundamental resonances at approx. 7.2 GHz and well defined harmonic resonances at approx. 14.4 and approx. 21.6 GHz, were designed, simulated and tested. For one of the filters, experimental results verified that its center frequency was tunable by 528 MHz at a center frequency of 21.957 GHz, with insertion losses varying from 4.3 to 2.5 dB, at 0 and 3.5 V/micron, respectively. These data demonstrate that the tuning-to-loss figure of merit of tunable microstrip filters can be greatly improved using patterned ferroelectric thin films as the tuning element, and tuning can be controlled by engineering the ferroelectric constriction in the coupled sections.

Miranda, Felix A.↗
NASA NTRS1992

Enhanced fatigue and retention in ferroelectric thin film memory capacitors by post-top electrode anneal treatment

Thin film ferroelectric capacitors comprising a ferroelectric film sandwiched between electrodes for nonvolatile memory operations are rendered more stable by subjecting the capacitors to an anneal following deposition of the top electrode. The anneal is done so as to form the interface between the ferroelectric film and the top electrode. Heating in an air oven, laser annealing, or electron bombardment may be used to form the interface. Heating in an air oven is done at a temperature at least equal to the crystallization temperature of the ferroelectric film. Where the ferroelectric film comprises lead zirconate titanate, annealing is done at about 550 to 600 C for about 10 to 15 minutes. The formation treatment reduces the magnitude of charge associated with the nonswitching pulse in the thin film ferroelectric capacitors. Reduction of this charge leads to significantly more stable nonvolatile memory operations in both digital and analog memory devices. The formation treatment also reduces the ratio of change of the charge associated with the nonswitching pulse as a function of retention time. These improved memory devices exhibit greater performance in retention and reduced fatigue in memory arrays.

Thakoor, Sarita↗
NASA NTRS1999

Thin-Film Ferroelectric Tunable Microwave Devices Being Developed

Electronically tunable microwave components have become the subject of intense research efforts in recent years. Many new communications systems would greatly benefit from these components. For example, planned low Earth orbiting satellite networks have a need for electronically scanned antennas. Thin ferroelectric films are one of the major technologies competing to fill these applications. When a direct-current (dc) voltage is applied to ferroelectric film, the dielectric constant of the film can be decreased by nearly an order of magnitude, changing the high-frequency wavelength in the microwave device. Recent advances in film growth have demonstrated high-quality ferroelectric thin films. This technology may allow microwave devices that have very low power and are compact, lightweight, simple, robust, planar, voltage tunable, and affordable. The NASA Lewis Research Center has been designing, fabricating, and testing proof-of-concept tunable microwave devices. This work, which is being done in-house with funding from the Lewis Director's Discretionary Fund, is focusing on introducing better microwave designs to utilize these materials. We have demonstrated Ku- and K-band phase shifters, tunable local oscillators, tunable filters, and tunable diplexers. Many of our devices employ SrTiO3 as the ferroelectric. Although it is one of the more tunable and easily grown ferroelectrics, SrTiO3 must be used at cryogenic temperatures, usually below 100 K. At these temperatures, we frequently use high-temperature superconducting thin films of YBa2Cu3O7-8 to carry the microwave signals. However, much of our recent work has concentrated on inserting room-temperature ferroelectric thin films, such as BaxSr1- xTiO3 into these devices. The BaxSr1-xTiO3 films are used in conjuction with normal metal conductors, such as gold.

VanKeuls, Frederick W.↗
NASA NTRS1994

Enhanced fatigue and retention in ferroelectric thin film memory capacitors by post-top electrode anneal treatment

Thin film ferroelectric capacitors (10) comprising a ferroelectric film (18) sandwiched between electrodes (16 and 20) for nonvolatile memory operations are rendered more stable by subjecting the capacitors to an anneal following deposition of the top electrode (20). The anneal is done so as to form the interface (22) between the ferroelectric film and the top electrode. Heating in an air oven, laser annealing, or electron bombardment may be used to form the interface. Heating in an air oven is done at a temperature at least equal to the crystallization temperature of the ferroelectric film. Where the ferroelectric film comprises lead zirconate titanate, annealing is done at about 550.degree. to 600.degree. C. for about 10 to 15 minutes. The formation treatment reduces the magnitude of charge associated with the non-switching pulse in the thin film ferroelectric capacitors. Reduction of this charge leads to significantly more stable nonvolatile memory operations in both digital and analog memory devices. The formation treatment also reduces the ratio of change of the charge associated with the non-switching pulse as a function of retention time. These improved memory devices exhibit greater performance in retention and reduced fatigue in memory arrays.

Thakoor, Sarita↗
NASA NTRS1982

Performing spectroscopic and specific heat studies of improper ferroelectrics

The results of infrared measurements on Ni-Br, Cu-Cl, and Fe-I boracite improper ferroelectrics and far infrared measurements of Ni-Br boracite are presented. The boracites have the general formula X3B7O3Y, where X = divalent metal and Y = halogen. They undergo a first order phase transition from a high temperature paraelectric phase with cubic symmetry to a ferroelectric phase with orthorhombic symmetry. The boracites are "improper ferroelectrics" since the spontaneous polarization is not the primary order parameter in the cubic-orthorhombic phase transition. Current understanding of these materials is that the primary order parameter is associated with a doubly degenerate zone-boundary phonon in the cubic phase. The degenerate critical modes become homogeneous and split into the A sub 1 and A sub 2 modes in the orthorhombic phase, doubling the volume of the primitive cell. An harmonic coupling between the softing A sub 1 and a low frequency A sub 1 optic mode induces a spontaneous polarization as a secondary effect in the ferroelectric phase. This secondary non-critical nature of the ferroelectric mode earns these materials the "improper" title and is responsible for their unique properties and high figure of merit in detector use.

Coleman, L. B.↗
NASA NTRS1995

Thin Layer Composite Unimorph Ferroelectric Driver and Sensor

A method for forming ferroelectric wafers is provided. A prestress layer is placed on the desired mold. A ferroelectric wafer is placed on top of the prestress layer. The layers are heated and then cooled, causing the ferroelectric wafer to become prestressed. The prestress layer may include reinforcing material and the ferroelectric wafer may include electrodes or electrode layers may be placed on either side of the ferroelectric layer. Wafers produced using this method have greatly improved output motion.

Helbaum, Richard F.↗
NASA NTRS1997

Thin Layer Composite Unimorph Ferroelectric Driver and Sensor

A method for forming ferroelectric wafers is provided. A prestress layer is placed on the desired mold. A ferroelectric wafer is placed on top of the prestress layer. The layers are heated and then cooled causing the ferroelectric wafer to become prestressed. The prestress layer may include reinforcing material and the ferroelectric wafer may include electrodes or electrode layers may be placed on either side of the ferroelectric layer. Wafers produced using this method have greatly improved output motion.

Hellbaum, Richard F.↗
NASA NTRS2000

Correlation Between Material Properties of Ferroelectric Thin Films and Design Parameters for Microwave Device Applications: Modeling Examples and Experimental Verification

The application of thin ferroelectric films for frequency and phase agile components is the topic of interest of many research groups worldwide. Consequently, proof-of-concepts (POC) of different tunable microwave components using either (HTS, metal)/ferroelectric thin film/dielectric heterostructures or (thick, thin) film "flip-chip" technology have been reported. Either as ferroelectric thin film characterization tools or from the point of view of circuit implementation approach, both configurations have their respective advantages and limitations. However, we believe that because of the progress made so far using the heterostructure (i.e., multilayer) approach, and due to its intrinsic features such as planar configuration and monolithic integration, a study on the correlation of circuit geometry aspects and ferroelectric material properties could accelerate the insertion of this technology into working systems. In this paper, we will discuss our study performed on circuits based on microstrip lines at frequencies above 10 GHz, where the multilayer configuration offers greater ease of insertion due to circuit's size reduction. Modeled results of relevant circuit parameters such as the characteristic impedance, effective dielectric constant, and attenuation as a function of ferroelectric film's dielectric constant, tans, and thickness, will be presented for SrTiO3 and Ba(x)Sr(1-x)TiO3 ferroelectric films. A comparison between the modeled and experimental data for some of these parameters will be presented.

Miranda, Felix A.↗
NASA NTRS2004

Thin layer composite unimorph ferroelectric driver and sensor

A method for forming ferroelectric wafers is provided. A prestress layer is placed on the desired mold. A ferroelectric wafer is placed on top of the prestress layer. The layers are heated and then cooled, causing the ferroelectric wafer to become prestressed. The prestress layer may include reinforcing material and the ferroelectric wafer may include electrodes or electrode layers may be placed on either side of the ferroelectric layer. Wafers produced using this method have greatly improved output motion.

Hellbaum, Richard F.↗