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13 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

Electron-beam lithography for micro and nano-optical applications

Direct-write electron-beam lithography has proven to be a powerful technique for fabricating a variety of micro- and nano-optical devices. Binary E-beam lithography is the workhorse technique for fabricating optical devices that require complicated precision nano-scale features. We describe a bi-layer resist system and virtual-mark height measurement for improving the reliability of fabricating binary patterns. Analog E-beam lithography is a newer technique that has found significant application in the fabrication of diffractive optical elements. We describe our techniques for fabricating analog surface-relief profiles in E-beam resist, including some discussion regarding overcoming the problems of resist heating and charging. We also describe a multiple-field-size exposure scheme for suppression of field-stitch induced ghost diffraction orders produced by blazed diffraction gratings on non-flat substrates.

electron-beam lithography↗
NASA NTRS1994

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Sewell, James S.↗
NASA NTRS1994

Analog Phase Holograms by Electron Beam Lithography

Phase holograms have been created on the surface of a thin film of poly-methyl methacrylate (PMMA, Plexiglas) by direct-write electron beam (E-Beam) lithography. The process involves delivering a patterned exposure dose followed by partial development with a strong developer. The patterned dose derives from arbitrary computer-calculated holograms, which must be corrected for the sensitivity characteristic of the PMMA and for the effective point-spread function of the E-Beam.

phase↗
NASA NTRS2002

Fabrication of Tunnel Junctions For Direct Detector Arrays With Single-Electron Transistor Readout Using Electron-Beam Lithography

This paper will describe the fabrication of small aluminum tunnel junctions for applications in astronomy. Antenna-coupled superconducting tunnel junctions with integrated single-electron transistor readout have the potential for photon-counting sensitivity at sub-millimeter wavelengths. The junctions for the detector and single-electron transistor can be made with electron-beam lithography and a standard self-aligned double-angle deposition process. However, high yield and uniformity of the junctions is required for large-format detector arrays. This paper will describe how measurement and modification of the sensitivity ratio in the resist bilayer was used to greatly improve the reliability of forming devices with uniform, sub-micron size, low-leakage junctions.

Stevenson, T. R.↗
NASA NTRS2019

Fabrication of Phononic-Isolated Kinetic Inductance Detectors

Kinetic inductance detectors (KID) have received increased interest due to their relative ease of fabrication, low noise, and scalability to large format arrays required by next generation of astronomical telescopes. The development of KIDs has progressed rapidly, with very low noise equivalent power demonstrated by several groups and KIDs arrays implemented in several ground-based and air-borne instruments. In this paper, we describe a new fabrication process which consists of a membrane isolated KID incorporating a phononic bandgap structure tuned to block recombination phonons from escaping to the thermal bath. This architecture is designed to increase the quasi-particle lifetime and results in increased responsivity to signal photons and lower noise. These devices have been fabricated as lumped-element resonators with hafnium inductors and Nb capacitors on low stress silicon nitride and silicon-on-insulator membranes. We discuss the fabrication process, which uses a combination of sub-micron laser based direct write lithography and nanoscale electron beam lithography.

Denis, Kevin L.↗
NASA NTRS1993

Diffractive optics fabricated by direct write methods with an electron beam

State-of-the-art diffractive optics are fabricated using e-beam lithography and dry etching techniques to achieve multilevel phase elements with very high diffraction efficiencies. One of the major challenges encountered in fabricating diffractive optics is the small feature size (e.g. for diffractive lenses with small f-number). It is not only the e-beam system which dictates the feature size limitations, but also the alignment systems (mask aligner) and the materials (e-beam and photo resists). In order to allow diffractive optics to be used in new optoelectronic systems, it is necessary not only to fabricate elements with small feature sizes but also to do so in an economical fashion. Since price of a multilevel diffractive optical element is closely related to the e-beam writing time and the number of etching steps, we need to decrease the writing time and etching steps without affecting the quality of the element. To do this one has to utilize the full potentials of the e-beam writing system. In this paper, we will present three diffractive optics fabrication techniques which will reduce the number of process steps, the writing time, and the overall fabrication time for multilevel phase diffractive optics.

Kress, Bernard↗
NASA NTRS2000

Sub-Optical Lithography With Nanometer Definition Masks

Nanometer feature size lithography represents a major paradigm shift for the electronics and micro-electro-mechanical industries. In this paper, we discuss the capacity of dynamic focused reactive ion beam (FIB) etching systems to undertake direct and highly anisotropic erosion of thick evaporated gold coatings on boron-doped silicon X-ray mask membranes. FIB offers a new level of flexibility in micro fabrication, allowing for fast fabrication of X-ray masks, where pattern definition and surface alteration are combined in the same step which eliminates the whole lithographic process, in particular resist, resist development, electro-deposition and resist removal. Focused ion beam diameters as small as 7 nm can be obtained enabling fabrication well into the sub-20 nm regime. In preliminary demonstrations of this X-ray mask fabrication technique 22 nm width lines were milled directly through 0.9 microns of gold and a miniature mass spectrometer pattern was milled through over 0.5 microns of gold. Also presented are the results of the shadow printing, using the large depth of field of synchrotron high energy parallel X-ray beam, of these and other sub-optical defined patterns in photoresist conformally coated over surfaces of extreme topographical variation. Assuming that electronic circuits and/or micro devices scale proportionally, the surface area of devices processed with X-ray lithography and 20 nm critical dimension X-ray masks would be 0.5% that of contemporary devices (350 nm CD). The 20 CD mask fabrication represents an initial effort - a further factor of three reduction is anticipated which represents a further order-of-magnitude reduction in die area.

Hartley, Frank T.↗
NASA NTRS2010

Fabrication of Single, Vertically Aligned Carbon Nanotubes in 3D Nanoscale Architectures

Plasma-enhanced chemical vapor deposition (PECVD) and high-throughput manufacturing techniques for integrating single, aligned carbon nanotubes (CNTs) into novel 3D nanoscale architectures have been developed. First, the PECVD growth technique ensures excellent alignment of the tubes, since the tubes align in the direction of the electric field in the plasma as they are growing. Second, the tubes generated with this technique are all metallic, so their chirality is predetermined, which is important for electronic applications. Third, a wafer-scale manufacturing process was developed that is high-throughput and low-cost, and yet enables the integration of just single, aligned tubes with nanoscale 3D architectures with unprecedented placement accuracy and does not rely on e-beam lithography. Such techniques should lend themselves to the integration of PECVD grown tubes for applications ranging from interconnects, nanoelectromechanical systems (NEMS), sensors, bioprobes, or other 3D electronic devices. Chemically amplified polyhydroxystyrene-resin-based deep UV resists were used in conjunction with excimer laser-based (lambda = 248 nm) step-and-repeat lithography to form Ni catalyst dots = 300 nm in diameter that nucleated single, vertically aligned tubes with high yield using dc PECVD growth. This is the first time such chemically amplified resists have been used, resulting in the nucleation of single, vertically aligned tubes. In addition, novel 3D nanoscale architectures have been created using topdown techniques that integrate single, vertically aligned tubes. These were enabled by implementing techniques that use deep-UV chemically amplified resists for small-feature-size resolution; optical lithography units that allow unprecedented control over layer-to-layer registration; and ICP (inductively coupled plasma) etching techniques that result in near-vertical, high-aspect-ratio, 3D nanoscale architectures, in conjunction with the use of materials that are structurally and chemically compatible with the high-temperature synthesis of the PECVD-grown tubes. The techniques offer a wafer-scale process solution for integrating single PECVD-grown nanotubes into novel architectures that should accelerate their integration in 3D electronics in general. NASA can directly benefit from this technology for its extreme-environment planetary missions. Current Si transistors are inherently more susceptible to high radiation, and do not tolerate extremes in temperature. These novel 3D nanoscale architectures can form the basis for NEMS switches that are inherently less susceptible to radiation or to thermal extremes.

Kaul, Anupama B.↗
NASA NTRS2011

Carbon Nanotube-Based Structural Health Monitoring Sensors

Carbon nanotube (CNT)-based sensors for structural health monitoring (SHM) can be embedded in structures of all geometries to monitor conditions both inside and at the surface of the structure to continuously sense changes. These CNTs can be manipulated into specific orientations to create small, powerful, and flexible sensors. One of the sensors is a highly flexible sensor for crack growth detection and strain field mapping that features a very dense and highly ordered array of single-walled CNTs. CNT structural health sensors can be mass-produced, are inexpensive, can be packaged in small sizes (0.5 micron(sup 2)), require less power than electronic or piezoelectric transducers, and produce less waste heat per square centimeter than electronic or piezoelectric transducers. Chemically functionalized lithographic patterns are used to deposit and align the CNTs onto metallic electrodes. This method consistently produces aligned CNTs in the defined locations. Using photo- and electron-beam lithography, simple Cr/Au thin-film circuits are patterned onto oxidized silicon substrates. The samples are then re-patterned with a CNT-attracting, self-assembled monolayer of 3-aminopropyltriethoxysilane (APTES) to delineate the desired CNT locations between electrodes. During the deposition of the solution-suspended single- wall CNTs, the application of an electric field to the metallic contacts causes alignment of the CNTs along the field direction. This innovation is a prime candidate for smart skin technologies with applications ranging from military, to aerospace, to private industry.

Wincheski, Russell↗
NASA NTRS2007

Focal-Plane Arrays of Quantum-Dot Infrared Photodetectors

Focal-plane arrays of semiconductor quantum-dot infrared photodetectors (QDIPs) are being developed as superior alternatives to prior infrared imagers, including imagers based on HgCdTe devices and, especially, those based on quantum-well infrared photodetectors (QWIPs). HgCdTe devices and arrays thereof are difficult to fabricate and operate, and they exhibit large nonunformities and high 1/f (where f signifies frequency) noise. QWIPs are easier to fabricate and operate, can be made nearly uniform, and exhibit lower 1/f noise, but they exhibit larger dark currents, and their quantization only along the growth direction prevents them from absorbing photons at normal incidence, thereby limiting their quantum efficiencies. Like QWIPs, QDIPs offer the advantages of greater ease of operation, greater uniformity, and lower 1/f noise, but without the disadvantages: QDIPs exhibit lower dark currents, and quantum efficiencies of QDIPs are greater because the three-dimensional quantization of QDIPs is favorable to the absorption of photons at normal or oblique incidence. Moreover, QDIPs can be operated at higher temperatures (around 200 K) than are required for operation of QWIPs. The main problem in the development of QDIP imagers is to fabricate quantum dots with the requisite uniformity of size and spacing. A promising approach to be tested soon involves the use of electron-beam lithography to define the locations and sizes of quantum dots. A photoresist-covered GaAs substrate would be exposed to the beam generated by an advanced, high-precision electron beam apparatus. The exposure pattern would consist of spots typically having a diameter of 4 nm and typically spaced 20 nm apart. The exposed photoresist would be developed by either a high-contrast or a low-contrast method. In the high-contrast method, the spots would be etched in such a way as to form steep-wall holes all the way down to the substrate. The holes would be wider than the electron beam spots perhaps as wide as 15 to 20 nm, but may be sufficient to control the growth of the quantum dots. In the low-contrast method, the resist would be etched in such a way as to form dimples, the shapes of which would mimic the electron-beam density profile. Then by use of a transfer etching process that etches the substrate faster than it etches the resist, either the pattern of holes or a pattern comprising the narrow, lowest portions of the dimples would be imparted to the substrate. Having been thus patterned, the substrate would be cleaned. The resulting holes or dimples in the substrate would serve as nucleation sites for the growth of quantum dots of controlled size in the following steps. The substrate would be cleaned, then placed in a molecular-beam-epitaxy (MBE) chamber, where native oxide would be thermally desorbed and the quantum dots would be grown.

Gunapala, Sarath↗
NASA NTRS2004

Fabricating Blazed Diffraction Gratings by X-Ray Lithography

Gray-scale x-ray lithography is undergoing development as a technique for fabricating blazed diffraction gratings. As such, gray-scale x-ray lithography now complements such other grating-fabrication techniques as mechanical ruling, holography, ion etching, laser ablation, laser writing, and electron-beam lithography. Each of these techniques offers advantages and disadvantages for implementing specific grating designs; no single one of these techniques can satisfy the design requirements for all applications. Gray-scale x-ray lithography is expected to be advantageous for making gratings on steeper substrates than those that can be made by electron-beam lithography. This technique is not limited to sawtooth groove profiles and flat substrates: various groove profiles can be generated on arbitrarily shaped (including highly curved) substrates with the same ease as sawtooth profiles can be generated on flat substrates. Moreover, the gratings fabricated by this technique can be made free of ghosts (spurious diffraction components attributable to small spurious periodicities in the locations of grooves). The first step in gray-scale x-ray lithography is to conformally coat a substrate with a suitable photoresist. An x-ray mask (see Figure 1) is generated, placed between the substrate and a source of collimated x-rays, and scanned over the substrate so as to create a spatial modulation in the exposure of the photoresist. Development of the exposed photoresist results in a surface corrugation that corresponds to the spatial modulation and that defines the grating surface. The grating pattern is generated by scanning an appropriately shaped x-ray area mask along the substrate. The mask example of Figure 1 would generate a blazed grating profile when scanned in the perpendicular direction at constant speed, assuming the photoresist responds linearly to incident radiation. If the resist response is nonlinear, then the mask shape can be modified to account for the nonlinearity and produce a desired groove profile. An example of grating grooves generated by this technique is shown in Figure 2. A maximum relative efficiency of 88 percent has been demonstrated.

Mouroulis, Pantazis↗
NASA NTRS2005

Growing Aligned Carbon Nanotubes for Interconnections in ICs

A process for growing multiwalled carbon nanotubes anchored at specified locations and aligned along specified directions has been invented. Typically, one would grow a number of the nanotubes oriented perpendicularly to a silicon integrated-circuit (IC) substrate, starting from (and anchored on) patterned catalytic spots on the substrate. Such arrays of perpendicular carbon nanotubes could be used as electrical interconnections between levels of multilevel ICs. The process (see Figure 1) begins with the formation of a layer, a few hundred nanometers thick, of a compatible electrically insulating material (e.g., SiO(x) or Si(y)N(z) on the silicon substrate. A patterned film of a suitable electrical conductor (Al, Mo, Cr, Ti, Ta, Pt, Ir, or doped Si), having a thickness between 1 nm and 2 m, is deposited on the insulating layer to form the IC conductor pattern. Next, a catalytic material (usually, Ni, Fe, or Co) is deposited to a thickness between 1 and 30 nm on the spots from which it is desired to grow carbon nanotubes. The carbon nanotubes are grown by plasma-enhanced chemical vapor deposition (PECVD). Unlike the matted and tangled carbon nanotubes grown by thermal CVD, the carbon nanotubes grown by PECVD are perpendicular and freestanding because an electric field perpendicular to the substrate is used in PECVD. Next, the free space between the carbon nanotubes is filled with SiO2 by means of CVD from tetraethylorthosilicate (TEOS), thereby forming an array of carbon nanotubes embedded in SiO2. Chemical mechanical polishing (CMP) is then performed to remove excess SiO2 and form a flat-top surface in which the outer ends of the carbon nanotubes are exposed. Optionally, depending on the application, metal lines to connect selected ends of carbon nanotubes may be deposited on the top surface. The top part of Figure 2 is a scanning electron micrograph (SEM) of carbon nanotubes grown, as described above, on catalytic spots of about 100 nm diameter patterned by electron-beam lithography. These and other nanotubes were found to have lengths ranging from 2 to 10 m and diameters ranging from 30 to 200 nm, the exact values of length depending on growth times and conditions and the exact values of diameter depending on the diameters and thicknesses of the catalyst spots. The bottom part of Figure 2 is an SEM of an embedded array of carbon nanotubes after CMP.

Li, Jun↗