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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Design and performance of an in-vacuum, magnetic field mapping system for the Muon g-2 experiment

The Muon g - 2 experiment at Fermilab (E989) aims to measure the anomalous magnetic moment, a μ , of the muon with a precision of 140 parts-per-billion. This requires a precise measurement of both the anomalous spin precession frequency, ω α , of muons stored in a magnetic field of 1.45 T, and a precise measurement of that magnetic field in terms of the shielded proton Larmor frequency, ω' ρ . The measurement of ω' ρ with a total systematic uncertainty of 70 parts-perbillion involves a combination of various nuclear magnetic resonance (NMR) probes. There are 378 probes mounted in fixed locations that constantly monitor field drifts. A water-based, cylindrical calibration probe provides the calibration in terms of the shielded proton Larmor frequency. A crucial element for the multi-step measurement of ω' ρ is the regular mapping of the magnetic field over the muon storage region. The former experiment at Brookhaven National Laboratory (BNL) employed an in-vacuum field mapping system equipped with 17 NMR probes, which was developed by the University of Heidelberg. We have refurbished and upgraded this system with new probes and electronics. The upgrades include the addition of 16-bit, 1 MSPS digitization of the NMR signals, which replaced the hardware-implemented zero-crossing counting of the system at Brookhaven. The digitized signals offer new capabilities in the NMR frequency analysis and its related systematic uncertainties. To sustain the higher data rates, a new communication scheme with time-division multiplexing was implemented to separate the important NMR reference clock from the data communication in order to reach the specifications for the accuracy and stability of the reference clock. A new barcode reader provides more precise azimuthal position determination during the measurement and calibration. While the mechanical systems that move the field mapper inside the storage ring have been mostly refurbished from BNL, the motion control system was completely replaced with a custom-built electronics centered around a commercial Galil motion controller. Both the field mapping NMR system and its motion control were successfully commissioned at Fermilab and have been in reliable operation during the first three data taking periods of the experiment at Fermilab. Finally, this article will provide the details of the upgrades of the field mapper and its performance.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

An integer- N frequency synthesizer for flexible on-chip clock generation

A low-power integer-N frequency synthesizer for flexible on-chip clock generation has been designed in a 65 nm CMOS process. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and 3 GHz that are locked to a 10–50 MHz reference input. The design uses a phase-locked loop (PLL) with a dual-tuned LC voltage-controlled oscillator (VCO), programmable feedback divider, and dual output dividers. The total power consumption from 1.2 V and 0.8 V supplies is 4.0 mW. In conclusion, experimental results confirm the functionality of the proposed synthesizer over a wide range of output frequencies.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

The AMACStar ASIC for the HL-LHC ATLAS ITk Strip detector: design, verification, testing, and quality assurance

For the high-luminosity upgrade to the LHC (HL-LHC), the ATLAS detector at CERN requires an all-new inner detector, the Inner Tracker (ITk). The ITk Strip subdetector is made up of silicon modules, which include three types of radiation-hard ASICs. One of these is the Autonomous Monitor and Control (AMAC). The AMAC is manufactured by Global Foundries using 130 nm CMOS8RF DM technology and is approximately 3 by 5 mm in size. This ASIC autonomously monitors the temperatures, voltages, and currents in the module components while controlling critical values in order to prevent these quantities from reaching dangerous levels. The final design, AMACStar, was verified, tested, and ensured to perform all necessary functions. A quality control procedure using an in-house probe station set-up was developed in order to ensure that every individual chip on each wafer of AMACStars required by the ITk Strip project met performance requirements. The average per wafer yield of usable AMACStars is 92.33%, exceeding the design-specific 90% yield estimated for project costing. This estimate was based on actual yields for similar designs in this process.

Analogue electronic circuits↗
DOE OSTI2022

The CMS Barrel Calorimeter Processor demonstrator (BCPv1) board evaluation

For the CERN LHC phase 2, the barrel region of the CMS electromagnetic (ECAL EB) and hadronic calorimeters (HCAL HB) require new back-end electronics for their readout. To this purpose, a first version of the ATCA-based blade, the Barrel Calorimeter Processor (BCPv1), has been developed. The performance of the optical links as well as clock distribution are also presented here. Here, the BCPv1 has been tested together with front-end and trigger boards, as well as with the new DAQ and TCDS Hub (DTH) [1], to demonstrate that the BCPv1 meets the required specifications.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

Prototype hardware design and testing of the global common module for the global trigger subsystem of the ATLAS phase-II upgrade

We report the High-Luminosity Large Hadron Collider (HL-LHC) will deliver more than ten times the integrated luminosity of the previous runs combined. Meeting its stricter throughput requirements poses new challenges to the Trigger and Data Acquisition (TDAQ) systems of the LHC experiments. Introduced in the framework of the ATLAS experiment’s HL upgrade, the Global Trigger (GT) is a new subsystem which will perform offline-like algorithms on full-granularity calorimeter data. The implementation of the GT’s functionality is firmware-focused and is composed of three layers: multiplexing (or data aggregating), global event processing, and demultiplexing interface to the central trigger processor. Each layer will be composed of several, similar nodes, hosted on replicas of identical hardware, the Global Common Module (GCM), an ATCA front board which is designed to be adopted throughout the entire GT subsystem. This article proceeds from the TWEPP 2021 conference and presents the GCM hardware design, performed in 2020, and focuses on some key results of its extensive testing performed in 2021.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

TDC with uncontrolled delay lines: calibration approaches and precision improvement methods

The time-to-digital-converter (TDC) using uncontrolled delay lines has a simple structure and finer measurement precision since the delay cells are pure digital gates that operate at maximum speed. For every incoming hit, two “snapshots” of the delay line are taken by the register array with two strobes separated with a known time interval. With two measurements, propagation delays of each cell in the delay line can be calibrated for the operating temperature and voltage. The two measurements can also be averaged to improve the TDC measurement precision. We will discuss various calibration approaches and present test results in this work.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2022

A Low-Power 1 Gb/s Line Driver with Configurable Pre-Emphasis for Lossy Transmission Lines

A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization (FFE) architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval (UI) via an 8-stage delay-locked loop (DLL) and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated (SST) drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

Integration of EDWARD readout architecture in full-field fluorescence imaging detector

Data bandwidth, timing resolution and resource utilization in readouts of radiation detectors are a constant challenge. Event driven solutions are pushing against well-trenched framed solutions. The idea for an asynchronous readout architecture called EDWARD ( E vent- D riven W ith A ccess and R eset D ecoder) was presented at the TWEPP 2021 conference. Here we show the progress of our work which resulted in two chip prototypes. The first one, named 3FI65P1, is a full device with the analog pixel circuitry suited for full-field fluorescence imaging. It is already manufactured, and preliminary results are presented. Finally, the second chip, named EDWARD65P1, contains digital pulse generators with Poisson-exponential distribution in each pixel for extraction of the performance matrix of the EDWARD architecture alone.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Microwave microscope studies of trapped vortex dynamics in superconductors

Trapped vortices in superconductors introduce residual resistance in superconducting radio-frequency (SRF) cavities and disrupt the operation of superconducting quantum and digital electronic circuits. Understanding the detailed dynamics of trapped vortices under oscillating magnetic fields is essential for advancing these technologies. We have developed a near-field magnetic microwave microscope to study the dynamics of a limited number of trapped vortices under the probe when stimulated by a localized rf magnetic field. By measuring the local second-harmonic response (𝑃 2⁢f ) at subfemto-Watt levels, we isolate signals exclusively arising from trapped vortices, excluding contributions from surface defects and Meissner screening currents. Toy models of niobium superconductor hosting vortex pinning sites are introduced and studied with time-dependent Ginzburg-Landau (TDGL) simulations of probe/sample interaction to better understand the measured second-harmonic response. The simulation results demonstrate that the second-harmonic response of trapped vortex motion under a localized rf magnetic field shares key features with the experimental data. Here, this measurement technique provides access to vortex dynamics at the micrometer scale, such as depinning events and spatially resolved pinning properties, as demonstrated in measurements on a niobium film with an antidot flux pinning array.

43 PARTICLE ACCELERATORS↗
DOE OSTI2025

Event-driven readout development: testing of the EDWARD65P1 chip with integrated event generators

Building on a prototype readout integrated circuit for segmented silicon sensors with the EDWARD event-driven readout architecture, the front-end in each pixel was replaced by a hardware generator to verify readout performance, ensuring no data loss, consistent priority handling, and speed verification. Here, this generator produces Poisson-distributed readout requests with individually tunable rates per pixel via a digitally controlled oscillator. The resulting EDWARD65P1 test ASIC is a 32×32 pixel matrix with a 100 μm pitch, equipped with digital event generators simulating radiation hits at user-defined rates. Test results for this new design are presented.

47 OTHER INSTRUMENTATION↗
DOE OSTI2020

Fast inference of Boosted Decision Trees in FPGAs for particle physics

We describe the implementation of Boosted Decision Trees in the hls4ml library, which allows the translation of a trained model into FPGA firmware through an automated conversion process. Thanks to its fully on-chip implementation, hls4ml performs inference of Boosted Decision Tree models with extremely low latency. With a typical latency less than 100 ns, this solution is suitable for FPGA-based real-time processing, such as in the Level-1 Trigger system of a collider experiment. These developments open up prospects for physicists to deploy BDTs in FPGAs for identifying the origin of jets, better reconstructing the energies of muons, and enabling better selection of rare signal processes.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Production and tests of the ADDC for the Micromegas detector of the ATLAS New Small Wheel

The Large Hadron Collider (LHC) at CERN will perform a series of upgrades to allow luminosity increases during the next physics runs expected from 2022 on. These will also significantly increase the trigger rates of all the detectors. As part of the ATLAS Phase-I upgrade, the current Small Wheel muon detectors will be replaced with state-of-the-art New Small Wheel (NSW) detectors to cope with the increased luminosity of the LHC. The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data from the resistive Micro-Mesh Gaseous Structure (Micromegas) detectors of the NSW. The ART ASIC on the ADDC is a customdesigned chip to receive theAddress in Real Time (ART) signals from theVMMfront-end ASIC and perform hit-selection processing. The processed trigger data is then sent to the Trigger Processor (TP) through optical links. A total of 512 ADDCs will be installed on the detector close to the front-end boards. Therefore, those cards must be able to work properly in a high radiation and magnetic field environment. Furthermore, after four rounds of prototyping, the ADDC production was launched in January of 2019. 600 ADDC boards have been produced and tested with an automated test stand. This test setup can simulate the front-end signals and provide "Level-1 Data Driver Card" (L1DDC) functions as well as part of the TP functions. Thus, the ADDC functionality and stability can be verified without the remaining NSW electronics. This paper describes the ADDC hardware prototype development, radiation and integration testing, and the ADDC automated production test procedure.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2022

Event driven readout architecture with non-priority arbitration for radiation detectors

A novel event driven readout architecture, EDWARD (Event Driven with Access and 8 Reset Decoder) architecture, for highly granular pixel detectors is presented. It incorporates, inter alia, an asynchronous arbitration tree based on Seitz' arbiters, removing the need for an imposed prioritization scheme. It also provides protection against glitches during readout. The system allows not only reading pixel activities, but also retrieving additional data, both analog and digital, from the pixels. A novel in-channel logic allows the entire readout process to be split into consecutive phases for additional flexibility. All operations are controlled by only one edge of the clock signal, seen as an acknowledge token, so there is no dead time between readouts.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

A sub-picosecond digital clock monitoring system

We describe a low-cost system designed to monitor wander in digital clocks with a precision of ≤ 1 ps. With this system we have shown that it is possible to track phase variations at the sub-picosecond level by adding noise to a reference clock. As in many cases where a clock is part of a complex distribution network small changes in temperature and other effects can lead to small changes in the clock's phase. As a further demonstration of the system, we have used it to measure the phase changes induced in optical signals in fibers.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

An FPGA-based readout chip emulator for the CMS ETL detector upgrade

Here, we present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

AstroPix4 — a novel HV-CMOS sensor developed for space based experiments

For the proposed space based gamma-ray observatory All-sky Medium-Energy Gamma-ray Observatory eXplorer (AMEGO-X), a silicon tracker based on a novel High Voltage-CMOS (HV-CMOS) sensor called AstroPix, is currently being developed. Preliminary measurements with the first full reticle prototype AstroPix3 show that the power target of 1.5 mW/cm 2 can currently not be reached due to the digital consumption of 3.08 mW/cm 2 , while the analog power consumption of 1.04 mW/cm 2 and a break down voltage of over 350 V look promising. Based on these results, the design changes in AstroPix4, submitted in May 2023, are presented, containing changes to the time stamp generation and readout architecture. A digital power consumption below 0.25 mW/cm 2 is expected by removing the fast 200 MHz clock used to measure the time-over-threshold (ToT) and an LVDS receiver. A maximum resolution of 3.125 ns for time-of-arrival (ToA) and ToT is reached by adding per-pixel Flash-Time-to-Digital Converter (TDCs) controlled by a global delay-locked loop (DLL).

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

GaN HEMT Fabrication for Radiation-Hardened Sensing and Communications Electronics

Gallium nitride (GaN), a wide bandgap semiconductor, has vast potential to address two environment conditions associated with the application of electronics to nuclear power: elevated temperatures, and high levels of radiation. A process was developed at The Ohio State University (OSU) to enable fabrication of complex digital and analog electronics circuits for application to nuclear power environments such as locations near or in the reactor core or in spent nuclear fuel casks. Radio frequency (RF)-grade GaN high electron mobility transistor (HEMT) devices were fabricated as part of this process. These were fabricated as depletion mode and enhancement mode devices. They have been electrically characterized and have demonstrated the expected performance. Behavioral models (Verilog-A) were developed from these device measurements to enable electrical simulation of GaN HEMT devices and circuits using common electronics simulation tools based on Simulation Program with Integrated Circuit Emphasis (SPICE). A similar set of GaN HEMT devices is being developed to provide lower speed devices for logic and analog functions. These accomplishments position this technology for effective application to sensor interfacing, signal processing, and data communications in nuclear power plants, including operation in or near the reactor core.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2026

Advancements in NbTiN based circuits for Superconducting Digital Logic

Superconducting (SC) electronics have emerged as a promising platform for high-speed, energy-efficient computing and quantum information processing. This work, centered on NbTiN, presents recent advances in material science and fabrication methods leading to significant improvements in performance, scalability and vertical integration. We specifically report on fabrication and characterization of key components, including Josephson junctions (JJs), flux trapping structures and SC interconnects. Together, these efforts represent critical steps towards realizing practical, complex, dense and large-scale SC integrated circuits.

Pokhrel, A. [Imec,Heverlee,Belgium]↗