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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Architectural Implications of Neural Network Inference for High Data-Rate, Low-Latency Scientific Applications

With more scientific fields relying on neural networks (NNs) to process data incoming at extreme throughputs and latencies, it is crucial to develop NNs with all their parameters stored on-chip. In many of these applications, there is not enough time to go off-chip and retrieve weights. Even more so, off-chip memory such as DRAM does not have the bandwidth required to process these NNs as fast as the data is being produced (e.g., every 25 ns). As such, these extreme latency and bandwidth requirements have architectural implications for the hardware intended to run these NNs: 1) all NN parameters must fit on-chip, and 2) codesigning custom/reconfigurable logic is often required to meet these latency and bandwidth constraints. In our work, we show that many scientific NN applications must run fully on chip, in the extreme case requiring a custom chip to meet such stringent constraints.

Weng, Olivia↗
DOE OSTI2019

OT-$\mu$DTC, a test bench for testing CMS Outer Tracker Phase-2 module prototypes

The Compact Muon Solenoid (CMS) experiment plans to replace its strip tracker system with a completely new Outer Tracker system to cope with the higher luminosity, compared to Run 2 operation, provided by the HL-LHC. This CMS Phase-2 Outer Tracker will be build up from two types of modules both consisting out of two parallel silicon sensors separated by a few millimetres. To read out the two types of modules four Outer Tracker specific custom chips are required. This proceeding introduces the module concept, goes into more detail on the data path, discusses the test system (OT-$\mu$DTC) designed for testing prototypes based on these ASICs and gives examples of test results obtained with this test system.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

System-on-chip approach microwave imaging reflectometer on DIII-D tokamak

System-on-chip millimeter wave integrated circuit technology is used on the two-dimensional millimeter-wave imaging reflectometer (MIR) upgrade for density fluctuation imaging on the DIII-D tokamak fusion plasma. Customized CMOS chips have been successfully developed for the transmitter module and receiver module array, covering the 55–75 GHz working band. The transmitter module has the capability of simultaneously launching eight tunable probe frequencies (>0 dBm output power each). The receiver enclosure contains 12 receiver modules in two vertical lines. The quasi-optical local oscillator coupling of previous MIR systems has been replaced with an internal active frequency multiplier chain for improved local oscillator power delivery and flexible installation in a narrow space together with improved shielding against electromagnetic interference. The 55–75 GHz low noise amplifier, used between the receiver antenna and the first-stage mixer, significantly improves module sensitivity and suppresses electronics noise. The receiver module has a 20 dB gain improvement compared with the mini-lens approach and better than –75 dBm sensitivity, and its electronics noise temperature has been reduced from 55 000 K down to 11 200 K. Further, the V-band MIR system is developed for co-located multi-field investigation of MHD-scale fluctuations in the pedestal region with W-band electron cyclotron emission imaging on DIII-D tokamak.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2018

Accelerated Architectures Create Programming Opportunities

In the early 2000s, industry switched to multicore microprocessors to address semiconductors' speed and power limits. However, the change was unsuccessful, leading to dire claims that “Moore's law is ending.” In conclusion, this column suggests that while the approach was sound, it needed a deeper architectural transformation. Industry has since discovered a suitable architecture, but work remains on software to support it.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

China’s Bid To Lead Artificial Intelligence Chip Development within the Decade

In 2017, the Chinese government announced an ambitious, broad strategy to become the global leader in artificial intelligence (AI) theories, technologies, and applications by 2030 and indicated that China’s ability to indigenously produce cutting-edge AI chips would be integral to its success. China’s goal to become a dominant producer of AI hardware within a decade is a bold undertaking because China faces domestic chip production challenges and fierce competition from US chip producers. Our review of Chinese AI chip product lines shows various levels where Chinese companies compete with global firms in the production chain. China lacks a robust indigenous AI chip production infrastructure, and the United States and its allies are tightening controls on the supply of advanced semiconductor manufacturing equipment (SME) and electronic design automation (EDA) software to China. In contrast to their Chinese counterparts, US companies operate in all areas of AI chip production and have consistently driven the development of new chip designs. AI chip production is a costly endeavor, and China’s chip producers currently lack the customer base to lead global AI chip development by the 2030 goal. An expanded customer base may help China attract the necessary expertise to bolster its AI chip production chain. This would also help Chinese producers make their investments in the requisite technology economically sustainable. Chinese researchers continue to pursue promising next-generation AI chip designs, such as neuromorphic computing-based architectures, which in the next five to ten years could position Chinese companies to make or contribute to key innovations in the field.

74 ATOMIC AND MOLECULAR PHYSICS↗
DOE OSTI2024

Mixed domain coherent link with electrically reconfigurable IMDD and coherent modes for O-band data center applications

We report the first O-band link with electrically reconfigurable intensity-modulation direct-detection (IMDD) and coherent operation using custom silicon photonic chips packaged with commercial electronic chips. Transmission below the KP4-FEC threshold is shown using commercial 53 Gbaud PAM4 digital signal processing (DSP) for 16QAM (200 Gbps/ λ ) and PAM4 (100 Gbps/ λ ). Efficient operation of the packaged full link at 12 and 11.2 pJ/bit is achieved for the PAM4 and 16QAM modes, respectively.

Misak, Stephen (ORCID:0000000154973084)↗
DOE OSTI2021

System-on-Chip approach microwave diagnostics development for burning plasma

System-on-chip (SoC) millimeter wave integrated circuit technology has been developed and employed in chip heterodyne radiometers in Electron Cyclotron Emission Imaging (ECEI) and Microwave Imaging Reflectometer (MIR) on the DIII-D tokamak for 2D electron temperature and density fluctuation diagnostics. The W-band (75-110 GHz) ECEI system has been employed with 20 poloidal horn receiver modules with customized monolithic integrated circuit chips and internal local oscillator coupling path. The new SoC approach demonstrates > 30 dB additional gain on the receiver and 95% electronics noise suppression compared to the previous Schottky diode mixer array . An F-band (110-140 GHz) receiver chip has been developed to measure MHD and turbulence behavior on the DIII-D high-field side, such as Alfven eigenmodes. Furthermore, it can image pedestal structure evolution on fusion facilities with stronger magnetic fields, such as ASDEX-U, EAST, HL-2M, and LHD. The F-band chip performance has been tested in the laboratory. Also, V-band (55-75 GHz) transmitter and receiver modules (55-75 GHz) have been developed for DIII-D and NSTX-U Furthermore, microwave Imaging Reflectometer (MIR) application suitability for 2D density fluctuation imaging on the pedestal region.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2023

A user-friendly plug-and-play cyclic olefin copolymer-based microfluidic chip for room-temperature, fixed-target serial crystallography

Over the past two decades, serial X-ray crystallography has enabled the structure determination of a wide range of proteins. With the advent of X-ray free-electron lasers (XFELs), ever-smaller crystals have yielded high-resolution diffraction and structure determination. A crucial need to continue advancement is the efficient delivery of fragile and micrometre-sized crystals to the X-ray beam intersection. This paper presents an improved design of an all-polymer microfluidic `chip' for room-temperature fixed-target serial crystallography that can be tailored to broadly meet the needs of users at either synchrotron or XFEL light sources. The chips are designed to be customized around different types of crystals and offer users a friendly, quick, convenient, ultra-low-cost and robust sample-delivery platform. Compared with the previous iteration of the chip [Gilbile et al. (2021), Lab Chip , 21 , 4831–4845], the new design eliminates cleanroom fabrication. It has a larger imaging area to volume, while maintaining crystal hydration stability for both in situ crystallization or direct crystal slurry loading. Crystals of two model proteins, lysozyme and thaumatin, were used to validate the effectiveness of the design at both synchrotron (lysozyme and thaumatin) and XFEL (lysozyme only) facilities, yielding complete data sets with resolutions of 1.42, 1.48 and 1.70 Å, respectively. Overall, the improved chip design, ease of fabrication and high modifiability create a powerful, all-around sample-delivery tool that structural biologists can quickly adopt, especially in cases of limited sample volume and small, fragile crystals.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2024

Investigating resource-efficient neutron/gamma classification ML models targeting eFPGAs

There has been considerable interest and resulting progress in implementing machine learning (ML) models in hardware over the last several years from the particle and nuclear physics communities. A big driver has been the release of the Python package, hls4ml, which has enabled porting models specified and trained using Python ML libraries to register transfer level (RTL) code. So far, the primary end targets have been commercial field-programmable gate arrays (FPGAs) or synthesized custom blocks on application specific integrated circuits (ASICs). However, recent developments in open-source embedded FPGA (eFPGA) frameworks now provide an alternate, more flexible pathway for implementing ML models in hardware. These customized eFPGA fabrics can be integrated as part of an overall chip design. In general, the decision between a fully custom, eFPGA, or commercial FPGA ML implementation will depend on the details of the end-use application. In this work, we explored the parameter space for eFPGA implementations of fully-connected neural network (fcNN) and boosted decision tree (BDT) models using the task of neutron/gamma classification with a specific focus on resource efficiency. We used data collected using an AmBe sealed source incident on Stilbene, which was optically coupled to an OnSemi J-series silicon photomultiplier (SiPM) to generate training and test data for this study. We investigated relevant input features and the effects of bit-resolution and sampling rate as well as trade-offs in hyperparameters for both ML architectures while tracking total resource usage. The performance metric used to track model performance was the calculated neutron efficiency at a gamma leakage of 10 -3 . The results of the study will be used to aid the specification of an eFPGA fabric, which will be integrated as part of a test chip.

47 OTHER INSTRUMENTATION↗
DOE OSTI2018

LArPix: demonstration of low-power 3D pixelated charge readout for liquid argon time projection chambers

In this work, we report the demonstration of a low-power pixelated readout system designed for three-dimensional ionization charge detection and digital readout of liquid argon time projection chambers (LArTPCs) . Unambiguous 3D charge readout was achieved using a custom-designed system-on-a-chip ASIC (LArPix) to uniquely instrument each pad in a pixelated array of charge-collection pads. The LArPix ASIC, manufactured in 180 nm bulk CMOS, provides 32 channels of charge-sensitive amplification with self-triggered digitization and multiplexed readout at temperatures from 80 K to 300 K . Using an 832-channel LArPix-based readout system with 3 mm spacing between pads, we demonstrated low-noise (0<50 e - RMS equivalent noise charge) and very low-power (<100 μW/channel) ionization signal detection and readout . The readout was used to successfully measure the three-dimensional ionization distributions of cosmic rays passing through a LArTPC, free from the ambiguities of existing projective techniques. The system design relies on standard printed circuit board manufacturing techniques, enabling scalable and low-cost production of large-area readout systems using common commercial facilities. This demonstration overcomes a critical technical obstacle for operation of LArTPCs in high-occupancy environments, such as the near detector site of the Deep Underground Neutrino Experiment (DUNE) .

47 OTHER INSTRUMENTATION↗
DOE OSTI2020

Design and Testing of the Address in Real-Time Data Driver Card for the Micromegas Detector of the ATLAS New Small Wheel Upgrade

The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data in the Micro-Mesh Gaseous Structure (Micromegas) detector of the ATLAS New Small Wheel (NSW) upgrade. The Address in Real Time (ART) signals are generated by the front-end ASIC, named VMM chip, to indicate the address of the first above-threshold event. A custom ASIC (ART ASIC) is designed to receive the ART signals from the VMM chip and implement the hit-selection. The processed data from the ART ASIC will be transmitted out of the NSW through the GBTx serializer, the unidirectional Versatile Twin Transmitter (VTTx) and fiber optical links. The ART signal is critical for the ATLAS experiment trigger selection thus the performance and stability of the ADDC is very important. To ensure extensive testing of the ADDC, an FPGA Mezzanine Card (FMC) based testing platform and a special designed firmware/software are developed. We find that this test platform works with the commercial Xilinx VC707 FPGA development kit, independent of the other electronics of the NSW it can test all the functions of the ADDC and its long-term stability. This paper will introduce the design, testing procedure and results of the ADDC and the FMC testing platform.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2021

Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication.

There is a growing interest in custom spatial accelerators for machine learning applications. These accelerators employ a spatial array of processing elements (PEs) interacting via custom buffer hierarchies and networks-on-chip. The efficiency of these accelerators comes from employing optimized dataflow (i.e., spatial/temporal partitioning of data across the PEs and fine-grained scheduling) strategies to optimize data reuse. The focus of this work is to evaluate these accelerator architectures using a tiled general matrix-matrix multiplication (GEMM) kernel. To do so, we develop a framework that finds optimized mappings (dataflow and tile sizes) for a tiled GEMM for a given spatial accelerator and workload combination, leveraging an analytical cost model for runtime and energy. Finally, our evaluations over five spatial accelerators demonstrate that the tiled GEMM mappings systematically generated by our framework achieve high performance on various GEMM workloads and accelerators.

42 ENGINEERING↗
DOE OSTI2021

Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication

There is a growing interest in custom spatial accelerators for machine learning applications. These accelerators employ a spatial array of processing elements (PEs) interacting via custom buffer hierarchies and networks-on-chip. The efficiency of these accelerators comes from employing optimized dataflow (i.e., spatial/temporal partitioning of data across the PEs and fine-grained scheduling) strategies to optimize data reuse. The focus of this work is to evaluate these accelerator architectures using a tiled general matrix-matrix multiplication (GEMM) kernel. To do so, we develop a framework that finds optimized mappings (dataflow and tile sizes) for a tiled GEMM for a given spatial accelerator and workload combination, leveraging an analytical cost model for runtime and energy. Our evaluations over five spatial accelerators demonstrate that the tiled GEMM mappings systematically generated by our framework achieve high performance on various GEMM workloads and accelerators.

43 PARTICLE ACCELERATORS↗
DOE OSTI2020

1.2 kV, 10 A, 4H-SiC Bi-Directional Field Effect Transistor (BiDFET) with Low On-State Voltage Drop

Bidirectional power switches are used in matrix-or cyclo-converters and in multistage inverter circuits to facilitate high-frequency AC-to-AC conversion. A new 1.2 kV bidirectional MOSFET (BiDFET) with low on-resistance is achieved and demonstrated using two discrete SiC power MOSFET bare die chips, packaged within a four-terminal custom-designed module. Static and dynamic characterization has been carried out to inspect the on-state and switching behaviour of the BiDFET. Here, the BiDFET is shown to have a low forward voltage drop of 0.6 V at a current of 10 A, which is more than 2.5x smaller than previous Si IGBT and SiC MOSFET based bidirectional switch implementations.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Physical Testing of The PSEC5 ASIC

The PSEC5 ASIC is a high-speed waveform sampling chip designed for ultra-fast timing detectors, offering up to 40 GSPS sampling with 10-bit resolution. This makes it well-suited for applications requiring fine time resolution, such as MCPs and LGADs. This work focuses on the physical testing and validation of the chip s internal clocking and SPI-controlled registers. Testing began with inspection of schematics and the prototype to identify and resolve design issues. Then, custom firmware was developed for an Arduino controller to interface with the chip via SPI, enabling read and write access to key control registers. Results confirm that the VCO operates between ~3.2 4.0 GHz and remains stable under non-VCOVDD fluctuations. The Division Ratio register enables frequency division by known factors (256, 128, 64, etc.), indicating a pre-division frequency of 3.2 GHz when the digital band is unmodified. While most registers responded correctly, some issues were observed, including unexpected current draw and unstable discriminator behavior. Overall, the chip shows promising functionality, but further work is needed to understand the state of the read only registers and address the existing issues. Continued testing and firmware development will be critical to ensuring reliable integration into detector systems.

Fahey, Alexander [Unlisted, US]↗
DOE OSTI2021

System-on-chip upgrade of millimeter-wave imaging diagnostics for fusion plasma

Monolithic, millimeter wave “system-on-chip” technology has been employed in chip heterodyne radiometers in a newly developed Electron Cyclotron Emission Imaging (ECEI) system on the DIII-D tokamak for 2D electron temperature and fluctuation diagnostics. The system employs 20 horn-waveguide receiver modules each with customized W-band (75–110 GHz) monolithic microwave integrated circuit chips comprising a W-band low noise amplifier, a balanced mixer, a ×2 local oscillator (LO) frequency doubler, and two intermediate frequency amplifier stages in each module. Compared to previous quasi-optical ECEI arrays with Schottky mixer diodes mounted on planar antennas, the upgraded W-band array exhibits >30 dB additional gain and 20× improvement in noise temperature; an internal eight times multiplier chain is used to provide LO coupling, thereby eliminating the need for quasi-optical coupling. The horn-waveguide shielding housing avoids out-of-band noise interference on each module. The upgraded ECEI system plays an important role for absolute electron temperature and fluctuation measurements for edge and core region transport physics studies. An F-band receiver chip (up to 140 GHz) is under development for additional fusion facilities with a higher toroidal magnetic field. Visualization diagnostics provide multi-scale and multi-dimensional data in plasma profile evolution. Finally, a significant aspect of imaging measurement is focusing on artificial intelligence for science applications.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

A compact cold-atom interferometer with a high data-rate grating magneto-optical trap and a photonic-integrated-circuit-compatible laser system

Abstract The extreme miniaturization of a cold-atom interferometer accelerometer requires the development of novel technologies and architectures for the interferometer subsystems. Here, we describe several component technologies and a laser system architecture to enable a path to such miniaturization. We developed a custom, compact titanium vacuum package containing a microfabricated grating chip for a tetrahedral grating magneto-optical trap (GMOT) using a single cooling beam. In addition, we designed a multi-channel photonic-integrated-circuit-compatible laser system implemented with a single seed laser and single sideband modulators in a time-multiplexed manner, reducing the number of optical channels connected to the sensor head. In a compact sensor head containing the vacuum package, sub-Doppler cooling in the GMOT produces 15 μK temperatures, and the GMOT can operate at a 20 Hz data rate. We validated the atomic coherence with Ramsey interferometry using microwave spectroscopy, then demonstrated a light-pulse atom interferometer in a gravimeter configuration for a 10 Hz measurement data rate and T = 0–4.5 ms interrogation time, resulting in Δ g / g = 2.0 × 10 −6 . This work represents a significant step towards deployable cold-atom inertial sensors under large amplitude motional dynamics.

74 ATOMIC AND MOLECULAR PHYSICS↗