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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

A CSP-Based Agent Modeling Framework for the Cougaar Agent-Based Architecture

Cognitive Agent Architecture (Cougaar) is a Java-based architecture for large-scale distributed agent-based applications. A Cougaar agent is an autonomous software entity with behaviors that represent a real-world entity (e.g., a business process). A Cougaar-based Model Driven Architecture approach, currently under development, uses a description of system's functionality (requirements) to automatically implement the system in Cougaar. The Communicating Sequential Processes (CSP) formalism is used for the formal validation of the generated system. Two main agent components, a blackboard and a plugin, are modeled as CSP processes. A set of channels represents communications between the blackboard and individual plugins. The blackboard is represented as a CSP process that communicates with every agent in the collection. The developed CSP-based Cougaar modeling framework provides a starting point for a more complete formal verification of the automatically generated Cougaar code. Currently it is used to verify the behavior of an individual agent in terms of CSP properties and to analyze the corresponding Cougaar society.

Gracanin, Denis↗
NASA NTRS2000

Accelerated thermal and mechanical testing of CSP assemblies

Chip Scale Packages (CSP) are now widely used for many electronic applications including portable and telecommunication products. A test vehicle (TV-1) with eleven package types and pitches was built and tested by the JPL MicrotypeBGA Consortium during 1997 to 1999. Lessons learned by the team were published as a guidelines document for industry use. The finer pitch CSP packages which recently became available were indluded in the next test vehicle of the JPL CSP Consortium.

Chip Scale Package CSP thermal cycle fatigue solde↗
NASA NTRS2014

CSP: A Multifaceted Hybrid Architecture for Space Computing

Research on the CHREC Space Processor (CSP) takes a multifaceted hybrid approach to embedded space computing. Working closely with the NASA Goddard SpaceCube team, researchers at the National Science Foundation (NSF) Center for High-Performance Reconfigurable Computing (CHREC) at the University of Florida and Brigham Young University are developing hybrid space computers that feature an innovative combination of three technologies: commercial-off-the-shelf (COTS) devices, radiation-hardened (RadHard) devices, and fault-tolerant computing. Modern COTS processors provide the utmost in performance and energy-efficiency but are susceptible to ionizing radiation in space, whereas RadHard processors are virtually immune to this radiation but are more expensive, larger, less energy-efficient, and generations behind in speed and functionality. By featuring COTS devices to perform the critical data processing, supported by simpler RadHard devices that monitor and manage the COTS devices, and augmented with novel uses of fault-tolerant hardware, software, information, and networking within and between COTS devices, the resulting system can maximize performance and reliability while minimizing energy consumption and cost. NASA Goddard has adopted the CSP concept and technology with plans underway to feature flight-ready CSP boards on two upcoming space missions.

Reconfigurable↗
NASA NTRS2007

Mise en Scene: Conversion of Scenarios to CSP Traces for the Requirements-to-Design-to-Code Project

The "Requirements-to-Design-to-Code" (R2D2C) project at NASA's Goddard Space Flight Center is based on deriving a formal specification expressed in Communicating Sequential Processes (CSP) notation from system requirements supplied in the form of CSP traces. The traces, in turn, are to be extracted from scenarios, a user-friendly medium often used to describe the required behavior of computer systems under development. This work, called Mise en Scene, defines a new scenario medium (Scenario Notation Language, SNL) suitable for control-dominated systems, coupled with a two-stage process for automatic translation of scenarios to a new trace medium (Trace Notation Language, TNL) that encompasses CSP traces. Mise en Scene is offered as an initial solution to the problem of the scenarios-to-traces "D2" phase of R2D2C. A survey of the "scenario" concept and some case studies are also provided.

Carter. John D.↗
NASA NTRS1999

Review of Stack CSP Technologies

CSP is an emerging technology with significant potential growth in stacking. Many of the stacking techniques for conventional packages could be implemented for CSP once materials, process, and system development for finer features are developed.

3D CSP stack CSP Chip Scale Package MCM Mulitchip ↗
NASA NTRS1987

0.87-micron CSP diode lasers for spaceborne communications

Index-guided channeled-substrate-planar (CSP) AlGaAs diode lasers are being developed for reliable, high-power operation for use as sources in spaceborne optical communications systems. Although most work on this AlGaAs structure has been aimed at optimizing performance at output wavelengths less than 8400 A, emission in the 8700 A regime is also of interest. In particular, such wavelengths are required for use in the direct detection laser transceiver to be incorporated into NASA's advanced communications technology satellite, in order to avoid absorption of the light by the atmosphere when communicating with ground-based terminals. Lowest order spatial mode and substantially single longitudinal mode output has been observed in 0.87-micron CSP devices in excess of 50 mW cw and 100 mW 50 percent duty-cycle, with rms phase-front aberrations measured to be about lambda/40.

Carlin, D. B.↗
NASA NTRS1992

Double-Current-Confined CSP Laser

Improved channeled-substrate-planar (CSP) lasers that emit at wavelengths between 860 and 880 nm grown by liquid-phase epitaxy (LPE). Exhibit record high output powers and efficiencies, attained without sacrifice of desirable characteristics of lasers. In fabrication, second reverse-bias p/n junction incorporated to reduce required current. By incorporating two reverse-bias junctions in CSP structure, one doubly confines current. Lasers used eventually as sources of light in intersatellite communications systems and, specifically, NASA Advanced Communications Technology Satellite (ACTS) System.

Connolly, John C.↗
NASA NTRS2000

CSP Manufacturing Challenges and Assembly Reliability

Although the expression of CSP is widely used by industry from suppliers to users, its implied definition had evolved as the technology has matured. There are "expert definition"- package that is up to 1.5 time die- or "interim definition". CSPs are miniature new packages that industry is starting to implement and there are many unresolved technical issues associated with their implementation. For example, in early 1997, packages with 1 mm pitch and lower were the dominant CSPs, whereas in early 1998 packages with 0.8 mm and lower became the norm for CSPs. Other changes included the use of flip chip die rather than wire bond in CSP. Nonetheless the emerging CSPs are competing with bare die assemblies and are becoming the package of choice for size reduction applications. These packages provide the benefits of small size and performance of the bare die or flip chip, with the advantage of standard die packages. The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. This talk will cover specifically the experience of our consortium on technology implementation challenges, including design and build of both standard and microvia boards, assembly of two types of test vehicles, and the most current environmental thermal cycling test results.

Ghaffarian, Reza↗
NASA NTRS2009

Machine-Checkable Timed CSP

The correctness of safety-critical embedded software is crucial, whereas non-functional properties like deadlock-freedom and real-time constraints are particularly important. The real-time calculus Timed Communicating Sequential Processes (CSP) is capable of expressing such properties and can therefore be used to verify embedded software. In this paper, we present our formalization of Timed CSP in the Isabelle/HOL theorem prover, which we have formulated as an operational coalgebraic semantics together with bisimulation equivalences and coalgebraic invariants. Furthermore, we apply these techniques in an abstract specification with real-time constraints, which is the basis for current work in which we verify the components of a simple real-time operating system deployed on a satellite.

Goethel, Thomas↗
NASA NTRS2013

SequenceL: Automated Parallel Algorithms Derived from CSP-NT Computational Laws

With the introduction of new parallel architectures like the cell and multicore chips from IBM, Intel, AMD, and ARM, as well as the petascale processing available for highend computing, a larger number of programmers will need to write parallel codes. Adding the parallel control structure to the sequence, selection, and iterative control constructs increases the complexity of code development, which often results in increased development costs and decreased reliability. SequenceL is a high-level programming language that is, a programming language that is closer to a human s way of thinking than to a machine s. Historically, high-level languages have resulted in decreased development costs and increased reliability, at the expense of performance. In recent applications at JSC and in industry, SequenceL has demonstrated the usual advantages of high-level programming in terms of low cost and high reliability. SequenceL programs, however, have run at speeds typically comparable with, and in many cases faster than, their counterparts written in C and C++ when run on single-core processors. Moreover, SequenceL is able to generate parallel executables automatically for multicore hardware, gaining parallel speedups without any extra effort from the programmer beyond what is required to write the sequen tial/singlecore code. A SequenceL-to-C++ translator has been developed that automatically renders readable multithreaded C++ from a combination of a SequenceL program and sample data input. The SequenceL language is based on two fundamental computational laws, Consume-Simplify- Produce (CSP) and Normalize-Trans - pose (NT), which enable it to automate the creation of parallel algorithms from high-level code that has no annotations of parallelism whatsoever. In our anecdotal experience, SequenceL development has been in every case less costly than development of the same algorithm in sequential (that is, single-core, single process) C or C++, and an order of magnitude less costly than development of comparable parallel code. Moreover, SequenceL not only automatically parallelizes the code, but since it is based on CSP-NT, it is provably race free, thus eliminating the largest quality challenge the parallelized software developer faces.

Cooke, Daniel↗
NASA NTRS2000

Thermal cycling test results of CSP and RF assemblies

A JPL-led chip scale package (CSP) Consortium of enterprises, composed of representing agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.

chip scale package CSP thermal cycle solder joint ↗
NASA NTRS1999

CSP Assembly Reliability

Reviews the many factors that affect interconnect reliability of emerging chip scale package (CSP) assemblies. These include: package type, package build, board design, and assembly variables.

chip scale package CSP solder joint reliability th↗
NASA NTRS1998

Key Factors on CSP Assembly Reliability

Although the weakest link of CSP assembly reliability has been often internal package failure, solder joint fatigue is still considered to be the key factor for reliability.

CSP assembly reliability solder joints↗
NASA NTRS1999

CSP Assembly Reliability: Commercial and Harsh Environments

The JPL-led CSP Consortium of enterprises representing government agencies and private companies has jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.

chip scale package CSP Solder Joint Reliability Th↗
NASA NTRS1991

Improving the Reliability and Modal Stability of High Power 870 nm AlGaAs CSP Laser Diodes for Applications to Free Space Communication Systems

The operating characteristics (power-current, beam divergence, etc.) and reliability assessment of high-power CSP lasers is discussed. The emission wavelength of these lasers was optimized at 860 to 880 nm. The operational characteristics of a new laser, the inverse channel substrate planar (ICSP) laser, grown by metalorganic chemical vapor deposition (MOCVD), is discussed and the reliability assessment of this laser is reported. The highlights of this study include a reduction in the threshold current value for the laser to 15 mA and a degradation rate of less than 2 kW/hr for the lasers operating at 60 mW of peak output power.

Connolly, J. C.↗