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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1972

Dual redundant core memory systems

Electronic memory system consisting of series redundant drive switch circuits, triple redundant majority voted memory timing functions, and two data registers to provide functional dual redundancy is described. Signal flow through the circuits is illustrated and equence of events which occur within the memory system is explained.

Hull, F. E.↗
NASA NTRS2009

Multi-Core Processor Memory Contention Benchmark Analysis Case Study

Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

Simon, Tyler↗
NASA NTRS1974

An improved version of the table look-up algorithm for pattern recognition

The table look-up approach to pattern recognition has been used for 3 years at several research centers in a variety of applications. A new version has been developed which is faster, requires significantly less core memory, and retains full precision of the input data. The new version can be used on low-cost minicomputers having 32K words (16 bits each) of core memory and fixed-point arithmetic; no special-purpose hardware is required. An initial FORTRAN version of this system can classify an ERTS computer-compatible tape into 24 classes in less than 15 minutes.

Eppler, W. G.↗
NASA NTRS1971

Table look-up approach to pattern recognition.

The table look-up approach is based on prestoring in fast, random-access, core memory the desired answer (e.g., crop-type) for all combinations of multispectral scanner outputs from selected channels. Specifically, each set of measurements from a given point on the ground is interpreted as that address in core memory where the answer can be retrieved. Substituting the simple retrieval operation for the length y computations required by the conventional approach offers two advantages: (1) the processing time is reduced by more than an order of magnitude; (2) the multispectral scanner data can be processed by computers having minimal sophistication, complexity, and cost. These two advantages may make it possible to use an onboard computer to perform the classification function in flight.

Eppler, W. G.↗
DOE OSTI2022

Partial densities of states from x-ray absorption and Auger electron spectroscopy: Use of core-hole memory

Ag L 3 edge x-ray absorption and L 3 −M 4,5 M 4,5 Auger electron spectra have been measured and simulated for a variety of x-ray electric-field polarization and Auger electron emission directions. The theory relies on density-functional theory, use of the Bethe–Salpeter equation, atomic multiplet theory, and a simplified model for the Auger line shape and its dependence on photon energy. We also demonstrate that partial densities of states for dT 2g , dE g , and sA g symmetry partial-wave channels at the Ag site in the solid can be deduced from the experimental measurements with only atomic theoretical input, i.e., with no solid-state theory other than assuming a Fermi edge.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Programming Strategies for Irregular Algorithms on the Emu Chick

The Emu Chick prototype implements migratory memory-side processing in a novel hardware system. Rather than transferring large amounts of data across the system interconnect, the Emu Chick moves lightweight thread contexts to near-memory cores before the beginning of each remote memory read. Previous work has characterized the performance of the Chick prototype in terms of memory bandwidth and programming differences from more typical, non-migratory platforms, but there has not yet been an analysis of algorithms on this system. This work evaluates irregular algorithms that could benefit from the lightweight, memory-side processing of the Chick and demonstrates techniques and optimization strategies for achieving performance in sparse matrix-vector multiply operation (SpMV), breadth-first search (BFS), and graph alignment across up to eight distributed nodes encompassing 64 nodelets in the Chick system. We also define and justify relative metrics to compare prototype FPGA-based hardware with established ASIC architectures. The Chick currently supports up to 68x scaling for graph alignment, 80 MTEPS for BFS on balanced graphs, and 50% of measured STREAM bandwidth for SpMV.

Hein, Eric↗
NASA NTRS2008

Initial Performance Results on IBM POWER6

The POWER5+ processor has a faster memory bus than that of the previous generation POWER5 processor (533 MHz vs. 400 MHz), but the measured per-core memory bandwidth of the latter is better than that of the former (5.7 GB/s vs. 4.3 GB/s). The reason for this is that in the POWER5+, the two cores on the chip share the L2 cache, L3 cache and memory bus. The memory controller is also on the chip and is shared by the two cores. This serializes the path to memory. For consistently good performance on a wide range of applications, the performance of the processor, the memory subsystem, and the interconnects (both latency and bandwidth) should be balanced. Recognizing this, IBM has designed the Power6 processor so as to avoid the bottlenecks due to the L2 cache, memory controller and buffer chips of the POWER5+. Unlike the POWER5+, each core in the POWER6 has its own L2 cache (4 MB - double that of the Power5+), memory controller and buffer chips. Each core in the POWER6 runs at 4.7 GHz instead of 1.9 GHz in POWER5+. In this paper, we evaluate the performance of a dual-core Power6 based IBM p6-570 system, and we compare its performance with that of a dual-core Power5+ based IBM p575+ system. In this evaluation, we have used the High- Performance Computing Challenge (HPCC) benchmarks, NAS Parallel Benchmarks (NPB), and four real-world applications--three from computational fluid dynamics and one from climate modeling.

Saini, Subbash↗