Bridging Circuit and Materials Ontologies in the Language Model Era
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Physics - Condensed matter physics↗
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Circuit for providing variable waveform excitation
A circuit for testing an electronic component, such as a transformer, includes at least two power supplies and at least two H bridge circuits. A first H bridge circuit is conductively coupled in parallel to a first power supply. A second H bridge circuit is conductively coupled in parallel to a second power supply. The second H bridge circuit includes one or more anti-series diodes for preventing current from the first power supply from passing through the second H bridge circuit to the second power supply. The first H bridge circuit and the second H bridge circuit are configured to conductively couple to the electronic component for providing a voltage with a predefined waveform to the electronic component.
Beddingfield, Richard B.↗
Pop-up Langmuir probe diagnostic in the water cooled divertor of Wendelstein 7-X
The design, development, and successful implementation of pop-up Langmuir probes installed in the water-cooled divertor of W7-X are described. The probes are controlled by drive coils (actuators) installed behind the divertor plates. These drive coils make use of the magnetic field in W7-X to move the probe tips into and out of the plasma. The drive coils were installed in the vacuum vessel after extensively testing the durability of the coils and analyzing the criteria for safe operation. The probe design is carefully tailored for each of the 36 probe tips in order to be suitable for the different magnetic field configurations used in W7-X and ensure that the probes do not present leading edges to the magnetic flux tubes. An electronic bridge circuit is used for measurement to compensate for the effects of signal propagation time on the long cable lengths used. The diagnostic is integrated with the segment control of W7-X for automated operation and control of the diagnostic. The evaluation of the results from the plasma operation is presented after accounting for appropriate sheath expansion for negative bias voltage on the probes.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
Data Acquisition System Selection and Calibration of Resistive Moisture Content Measurements for Large-Scale Field Studies in Cold Climate Residential Building Envelope Performance
The residential building stock built before the energy codes were enforced has several significant inefficiency problems in terms of insulation and air leakage. To decrease these inefficiencies, building retrofits are necessary. However, if the envelope is not appropriately designed, excessive accumulation of moisture content and thus mold formation and decay inside the envelope layers can be a vital problem. This risk becomes higher, especially in extreme climate conditions such as cold winters and hot and humid summers as in some northern regions of the U.S. Field studies are essential to test the long-term hygrothermal performance of building envelopes. Although in-situ temperature, RH, and heat flux measurements are straightforward, moisture content measurements are cumbersome. Mainly, because of the heterogeneous nature of the wood materials, deviations and nonuniformities within the materials are unavoidable. Resistance measurements are one of the oldest methods used to measure the moisture content of wood and other building materials. In large-scale studies, it is commonly preferred to use multi-purpose data acquisition systems (DAQ) and custom-made or prefabricated moisture pins to measure the electrical resistance (and thus moisture content) of critical building materials. These multi-purpose DAQ systems generally provide lower costs and offer more flexibility. However, these systems require calibration and fine-tuning to achieve accurate moisture content measurements. A large-scale, two-year-long field study was conducted in northern Minnesota to monitor the hygrothermal performance of residential retrofit wall systems in cold climates. Two base case walls and sixteen different wall treatments were tested. Moisture contents were measured at various layers in each wall treatment using 85 sets of moisture pins. This paper focuses on the overall approach, fabrication, and calibration methodology for the combination of custom-made moisture pins and a multi-purpose DAQ. The aim is to directly use the low-excitation multi-purpose DAQ without any extra voltage regulator. A half-bridge circuit is used to measure wood resistance with 4V excitation voltage and 100 kΩ and 500 kΩ reference resistors. The system is calibrated for four different materials: Douglas fir, lodgepole pine, western red cedar, and oriented strand board (OSB). Calibration experiments were done under controlled conditions in 50% and 65% RH test chambers. Resistance-based moisture content calibration curves are obtained for each species. Results show that higher reference resistors provided better calibration curves for lower excitation voltages.
Desjarlais, Andre Omer↗
Towards Generalizable and Efficient Circuit Topology Design: A Graph-Transformer-based Surrogate Model with Curriculum Learning
Unlike circuit parameter and sizing optimizations, the automated design of analog circuit topologies poses significant challenges for learning-based approaches. One challenge arises from the combinatorial growth of the topology space with circuit size, which limits the topology optimization efficiency. Moreover, traditional circuit evaluation methods are time-consuming, while the presence of data discontinuity in the topology space makes the accurate prediction of circuit performance exceptionally difficult for unseen topologies. To tackle these challenges, we design a novel Graph-Transformer-based Network (GTN) as the surrogate model for circuit evaluation, offering a substantial acceleration in the speed of circuit topology optimization without sacrificing performance. Our GTN model architecture is designed to embed voltage changes in circuit loops and current flows in connected devices, enabling accurate performance predictions for circuits with unseen topologies. To address the cold start problem when scaling GTN to large-scale circuits, we further introduce a curriculum learning strategy that progressively trains GTN from small-scale to large-scale circuits. This approach enables the model to first learn fundamental physical principles from simpler topologies and gradually adapt to complex configurations, effectively bridging the circuit complexity gap and improving prediction accuracy. Taking the power converter circuit design as an experimental task, our GTN model significantly outperforms an analytical approach and baseline methods directly utilizing graph neural networks. Furthermore, GTN achieves less than 5% relative error and 196× speed-up compared with high-fidelity simulation. Notably, our GTN surrogate model empowers an automatic circuit design framework to discover circuits of comparable quality to those identified through high-fidelity simulation while reducing the time required by up to 98.2%. With curriculum learning, the enhanced GTN achieves a 51% improvement for performance prediction of large-scale circuits compared to the GTN model without this strategy. These advancements establish GTN as a scalable framework for automated analog circuit design across varying circuit complexity levels.
Lu, Haoshu [New Jersey Institute of Technology (NJ↗
A Bulk-Capacitance Reduction Method Using Self-Driven Thyristor for AC-DC Converters
Universal serial bus power delivery (USB-PD) fast chargers equipped with wide-bandgap devices are driven to higher power density and efficiency. Furthermore, the indispensable high-voltage bulk capacitors used to smooth the rectifier output could take 40% of the total system volume due to the large capacitance value required. This paper discussed a capacitor reduction method using a self-driven thyristor scheme comprised of only three components in total. No extra control circuit is needed. Circuit analysis and design equations are presented, and the design results are implemented in a 60-W GaN-based active-clamp flyback converter. The measurement results on the prototype show a 36.4% reduction of the bulk-capacitor size with similar efficiency compared to the conventional solution.
30 DIRECT ENERGY CONVERSION↗
A Dual-Active-Bridge Converter Employing a Variable Inductor Without an Auxiliary Circuit
This paper proposes a dual active bridge (DAB) converter employing a variable inductor (VI) without an auxiliary circuit. Unlike conventional VI-based designs that require an external DC bias circuit, the proposed DAB utilizes the input DC current itself as the bias source, enabling automatic inductance variation with load conditions. The inductance naturally increases at low power and decreases at high power, effectively extending the zero voltage switching (ZVS) range and reducing circulating current, respectively. The VI was experimentally implemented and characterized to obtain its inductance-current profile, which was then integrated into a PLECS model of the DAB converter for circuit and thermal simulations. Simulation results confirm that the proposed auxiliary-free VI-DAB converter achieves a wider ZVS range and lower circulating current compared with a conventional fixed-inductor DAB converter. By realizing a variable inductor without any auxiliary bias circuitry, the proposed approach maintains soft switching and reduces reactive current losses across a wide load range, leading to improved efficiency and simplified implementation.
Jo, Cheolhui [ORNL] (ORCID:0000000322692434)↗
Systematic evaluation of magnetic sensitivities of anisotropic magnetoresistive sensors at liquid helium temperature for superconducting cavities
Trapped magnetic flux in bulk superconductors reduces the quality factor Q in superconducting radio-frequency (SRF) cavities. However, the mechanisms underlying flux trapping and radio-frequency loss are not well understood. Detailed observation of the magnetic distributions is important for understanding such phenomena. Magnetic field mapping is useful for observing the magnetic field distribution around SRF cavities. Measuring the change in the magnetic field around the cavity elucidates the flux trapping behavior. Anisotropic magnetoresistive (AMR) sensors are inexpensive and small devices that can detect magnetic flux density. The magnetic sensitivities of AMR sensors need to be evaluated at liquid helium temperature for the magnetic field mapping of SRF cavities. In this study, a test stand was constructed to calibrate the magnetic sensitivities of AMR sensors in liquid helium, and 110 AMR sensors were tested using this stand. The magnetic sensitivities were evaluated systematically. A solenoid coil was used to control the uniform external magnetic field and to measure the magnetic sensitivity at low temperatures. All AMR sensors exhibited suitable sensitivities to the magnetic field around the SRF cavity. The variation in these sensitivities in all AMR sensors was ~1%. Further, the AMR sensors were found to have sufficient sensitivity for mapping the magnetic field around the exterior surface of the SRF cavity.
43 PARTICLE ACCELERATORS↗
A PCB-Embedded 1.2 kV SiC MOSFET Half-Bridge Package for a 22 kW AC–DC Converter
This article presents the design and analysis of a double-side-cooled printed circuit board (PCB) embedded silicon carbide (SiC) MOSFET half-bridge package with low loop inductances and an integrated gate driver. The 1.2 kV SiC MOSFET dies used in the half-bridge package are embedded in the PCB using AT&S's patented technique. The dies are cooled and electrically connected to traces in the PCB through copper-filled microvias. The design methodology accounts for both electrical and thermal performance, limiting the power-loop inductance to 2.3 nH and the maximum package temperature to less than the 175 °C limit. The integration of the gate drive circuitry allows for a high power density and 2.2 nH gate-loop inductances. At 0.12 K/W, the measured junction-to-case thermal resistance with double-sided cooling is 57% lower than that of a TO-247 package. Under similar operating conditions, the PCB-embedded half-bridge package also achieves a 5.6 times lower voltage overshoot and a 0.5% higher peak efficiency than a TO-247-based half-bridge. This article reports the first demonstration of PCB-embedded 1.2 kV SiC MOSFET packages in buck, boost, and ac–dc converters. Furthermore, the prototype three-phase ac–dc converter for an electric vehicle on-board charger is composed of six PCB-embedded half-bridge packages and achieves an efficiency of 98.2% and a power density of 182 W/in 3 .
42 ENGINEERING↗
Stress accommodation in nanoscale dolan bridges designed for superconducting qubits
Josephson junctions are the principal circuit element in numerous superconducting quantum information devices and can be readily integrated into large-scale electronics. However, device integration at the wafer scale necessarily depends on having a reliable, high-fidelity, and high-yield fabrication method for creating Josephson junctions. When creating Al/AlO x based superconducting qubits, the standard Josephson junction fabrication method relies on a sub-micron suspended resist bridge, known as a Dolan bridge, which tends to be particularly fragile and can often times fracture during the resist development process, ultimately resulting in device failure. In this work, we demonstrate a unique Josephson junction lithography mask design that incorporates stress-relief channels. Our simulation results show that the addition of stress-relief channels reduces the lateral stress in the Dolan bridge by more than 70% for all the bridge geometries investigated. In practice, our novel mask design significantly increased the survivability of the bridge during device processing, resulting in 100% yield for over 100 Josephson junctions fabricated.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
Controller Verification of a Smart-Grid Compatible 200 kHz Single-stage Photovoltaic Microinverter
This paper presents control system design, implementation, and experimental validation of a single-stage 400 W, 200 kHz solar photovoltaic (PV) microinverter using hardware-in-the-loop (HIL) and hardware testing. The selected circuit topology is based on a Gallium Nitride (GaN) direct-matrix based dual active bridge (DAB) converter with a low voltage active power decoupler (APD) circuit. Control performance is verified, smart-grid compatibility is tested, and circuit operation is confirmed. Controller HIL (CHIL) is shown to aid in a complex power electronics system design by 1) enabling detailed control development prior to hardware implementation, 2) expanding the use of automated testing, and 3) increasing confidence in control performance prior to prototype testing. Altogether, these factors make HIL a valuable tool in complex power electronic designs.
14 SOLAR ENERGY↗
QECC-Synth: A Layout Synthesizer for Quantum Error Correction Codes on Sparse Architectures
Quantum Error Correction (QEC) codes are essential for achieving fault-tolerant quantum computing (FTQC). However, their implementation faces significant challenges due to disparity between required dense qubit connectivity and sparse hardware architectures. Current approaches often either underutilize QEC circuit features or focus on manual designs tailored to specific codes and architectures, limiting their capability and generality. In response, we introduce QECC-Synth, an automated compiler for QEC code implementation that addresses these challenges. We leverage the ancilla bridge technique tailored to the requirements of QEC circuits and introduces a systematic classification of its design space flexibilities. We then formalize this problem using the MaxSAT framework to optimize these flexibilities. Evaluation shows that our method significantly outperforms existing methods while demonstrating broader applicability across diverse QEC codes and hardware architectures.
Yin, Keyi [University of California, San Diego]↗
Methods to Synchronize and Control the Secondary Side Active Rectifier in Wireless Power Transfer Systems
This paper presents practical analog circuit-based methods to synchronize the secondary side active bridge of different wireless power transfer (WPT) systems with their primary side. The synchronization is necessary for proper operation of any WPT system with an active bridge on the secondary. The proposed schemes use only secondary side signals without the need of any information from the primary side. Simulation results presented validate the proposed schemes.
Mukherjee, Subho↗
Efficiency Optimization of Dual Active Bridge Converter Based on dV/dt Snubber Capacitors
This paper presents a lossless regenerative dV/dt snubber circuit for PWM converters to achieve high-efficiency high power-density without significant cost and reliability penalties. The dV/dt snubber employs lossless capacitors for each MOSFET device in a converter to provide an additional path to store the switching energy during turn-off transient and decrease the actual turn-off loss of the MOSFET channel. A novel mathematical turn-off loss model is built to separate the actual turn-off loss of the MOSFET channel and the recycling switching energy stored in the total equivalent output capacitance including Coss, the dV/dt snubber, and etc. Necessary snubber optimization strategy is proposed in order to balance the turn-off loss with ZVS operation range and deadtime conduction loss, and thereby achieving an optimal efficiency performance. To prove the validity and accuracy of the novel turn-off loss model and optimization strategy, the dV/dt snubber has been incorporated into a 1.3kV/200kW DC/DC and a 1kV/70kVA DC/AC PWM converters. Experimental results are given to demonstrate the validity of the proposed dV/dt snubber capacitors and optimization strategy.
Xu, Wei↗
Integration of Ag-CBRAM crossbars and Mott ReLU neurons for efficient implementation of deep neural networks in hardware
In-memory computing with emerging non-volatile memory devices (eNVMs) has shown promising results in accelerating matrix-vector multiplications. However, activation function calculations are still being implemented with general processors or large and complex neuron peripheral circuits. Here, we present the integration of Ag-based conductive bridge random access memory (Ag-CBRAM) crossbar arrays with Mott rectified linear unit (ReLU) activation neurons for scalable, energy and area-efficient hardware (HW) implementation of deep neural networks. We develop Ag-CBRAM devices that can achieve a high ON/OFF ratio and multi-level programmability. Compact and energy-efficient Mott ReLU neuron devices implementing ReLU activation function are directly connected to the columns of Ag-CBRAM crossbars to compute the output from the weighted sum current. We implement convolution filters and activations for VGG-16 using our integrated HW and demonstrate the successful generation of feature maps for CIFAR-10 images in HW. Our approach paves a new way toward building a highly compact and energy-efficient eNVMs-based in-memory computing system.
Mott insulators↗
Performance trade-offs in reconfigurable networks for HPC
Designing efficient interconnects to support high-bandwidth and low-latency communication is critical toward realizing high performance computing (HPC) and data center (DC) systems in the exascale era. At extreme computing scales, providing the requisite bandwidth through overprovisioning becomes impractical. These challenges have motivated studies exploring reconfigurable network architectures that can adapt to traffic patterns at runtime using optical circuit switching. Despite the plethora of proposed architectures, surprisingly little is known about the relative performances and trade-offs among different reconfigurable network designs. We aim to bridge this gap by tackling two key issues in reconfigurable network design. First, we study how cost, power consumption, network performance, and scalability vary based on optical circuit switch (OCS) placement in the physical topology. Specifically, we consider two classes of reconfigurable architectures: one that places OCSs between top-of-rack (ToR) switches—ToR-reconfigurable networks (TRNs)—and one that places OCSs between pods of racks—pod-reconfigurable networks (PRNs). Second, we tackle the effects of reconfiguration frequency on network performance. Our results, based on network simulations driven by real HPC and DC workloads, show that while TRNs are optimized for low fan-out communication patterns, they are less suited for carrying high fan-out workloads. PRNs exhibit better overall trade-off, capable of performing comparably to a fully non-blocking fat tree for low fan-out workloads, and significantly outperform TRNs for high fan-out communication patterns.
Teh, Min Yee↗
A Novel Low-Profile High-Efficiency Three-Phase Matrix Transformer
High step-down isolated DC-DC conversion from an 800 V DC bus to low-voltage, high-current outputs is required in automotive auxiliary converters and data center power supplies. In such applications, conventional transformer-based converters require large turns ratios, which increase winding resistance, leakage inductance, and magnetic height. This paper proposes a novel low-profile three-phase matrix transformer that realizes a large effective voltage ratio through flux division among multiple secondary legs, without increasing the physical turns count of each winding. As a result, the proposed structure reduces copper usage and transformer height while preserving the voltage conversion capability of a conventional three-phase transformer. Finite element analysis shows that the proposed design reduces magnetic height by 27%, ferrite volume by 34%, and copper volume by 28%. Circuit-level simulations of an 800 V/12 V,3 kW CLLLC dual-active-bridge converter further show that the lower winding resistance reduces total system loss by 91% and increases DC-DC efficiency from 82.6% to 97.6% at 3 kW output.
Inoue, Shuntaro [ORNL] (ORCID:0000000262637627)↗
Circuit complexity and functionality: A statistical thermodynamics perspective
Circuit complexity, defined as the minimum circuit size required for implementing a particular Boolean computation, is a foundational concept in computer science. Determining circuit complexity is believed to be a hard computational problem. Recently, in the context of black holes, circuit complexity has been promoted to a physical property, wherein the growth of complexity is reflected in the time evolution of the Einstein-Rosen bridge (“wormhole”) connecting the two sides of an anti-de Sitter “eternal” black hole. Here, we are motivated by an independent set of considerations and explore links between complexity and thermodynamics for functionally equivalent circuits, making the physics-inspired approach relevant to real computational problems, for which functionality is the key element of interest. In particular, our thermodynamic framework provides an alternative perspective on the obfuscation of programs of arbitrary length—an important problem in cryptography—as thermalization through recursive mixing of neighboring sections of a circuit, which can be viewed as the mixing of two containers with “gases of gates.” This recursive process equilibrates the average complexity and leads to the saturation of the circuit entropy, while preserving functionality of the overall circuit. The thermodynamic arguments hinge on ergodicity in the space of circuits which we conjecture is limited to disconnected ergodic sectors due to fragmentation. The notion of fragmentation has important implications for the problem of circuit obfuscation as it implies that there are circuits of same size and functionality that cannot be connected via a polynomial number of local moves. Furthermore, we argue that fragmentation is unavoidable unless the complexity classes NP and coNP coincide, a statement that implies the collapse of the polynomial hierarchy of computational complexity theory to its first level.
Science & Technology - Other Topics↗