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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Layer-Dependent Bit Error Variation in 3-D NAND Flash Under Ionizing Radiation

In this paper, we studied the total ionization dose (TID) effects on the multilevel-cell (MLC) 3-D NAND flash memory using Co-60 gamma radiation. We found a significant page-to-page bit error variation within a physical memory block of the irradiated memory chip. Our analysis showed that the origin of the bit error variation is the unique vertical layer-dependent TID response of the 3-D NAND. We found that the memory pages located at the upper and lower layers of the 3-D stack show higher fails compared to the middle-layer pages of a given memory block. We confirmed our findings by comparing radiation response of four different chips of the same specification. In addition, we compared the TID response of the MLC 3-D NAND with that of the 2-D NAND chip, which showed less page-to-page variation in bit error within a given memory block. We discuss the possible application of our findings for the radiation-tolerant smart memory controller design.

3-D NAND flash↗
DOE OSTI2021

Bit error protection in cache memories

A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an error protection from among a plurality of error protections. The cache controller uses the selected error protection to protect the data stored in the portion of the cache memory from errors.

Kalamatianos, John↗
DOE OSTI2021

Analytical Bit-Error Model of NAND Flash Memories for Dosimetry Application

In this work, we provide an analytical model for the total ionizing dose (TID) effects on the bit error statistics of commercial flash memory chips. We have validated the model with experimental data collected by irradiating several commercial NAND flash memory chips from different technology nodes. We find that our analytical model can project bit errors at higher TID values (~ 20 krad(Si)) from measured data at lower TID values (<1 krad(Si)). Based on our model and the measured data, we have formulated basic design rules for using a commercial flash memory chip as a dosimeter. We discuss the impact of NAND chip-to-chip variability, noise margin and the intrinsic errors on the dosimeter design using detailed experimentation.

3-D NAND↗
DOE OSTI2023

OLCF Summit Supercomputer GPU Snapshots During Double-Bit Errors and Normal Operations

As we move into the exascale era, the power and energy footprints of high-performance computing (HPC) systems have grown significantly larger. Due to the harsh power and thermal conditions the system, components are exposed to extreme operating conditions. Operation of such modern HPC systems requires deep insights into long term system behavior to maintain its efficiency as well as its longevity. To help the HPC community to gain such insights, we provide double-bit errors using system telemetry data and logs collected from the Summit supercomputer, equipped with 27,648 Tesla V100 GPUs with 2nd-generation high-bandwidth memory (HBM2). The dataset relies on Nvidia XID records internally collected by GPU firmware at the time of failure occurrence, on the reboot-time logs of each Summit node, on node-level job scheduler records collected after each job termination, and on a 1Hz data rate from the baseboard management controllers (BMCs) of each Summit compute node using the OpenBMC event subscription protocol. Technical details can be found in the paper Oles et. al “Understanding GPU Memory Corruption at Extreme Scale: The Summit Case Study” ICS’24 (https://doi.org/10.1145/3650200.3656615).

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Masked fault detection for reliable low voltage cache operation

Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.

Ganapathy, Shrikanth↗
DOE OSTI2026

A scalable superconducting nanowire memory array with row–column addressing

Scalable superconducting memory is required for the development of low-energy superconducting computers and fault-tolerant quantum computers. Conventional superconducting logic-based memory cells possess a large footprint that limits scaling; nanowire-based superconducting memory cells, although more compact, have high error rates, which hinders integration into large arrays. Here we report a 4 × 4 superconducting nanowire memory array that is designed for scalable row–column operations and has a functional density of 2.6 Mbit cm −2 . Each memory cell is based on a nanowire loop consisting of two temperature-dependent superconducting switches and a variable kinetic inductor. The arrays operate at 1.3 K, where we implement and characterize multiflux quanta state storage and destructive read-out. By optimizing the write- and read-pulse sequences, we minimize bit errors and maximize operating margins. We achieve a minimum bit error rate of 10 −5 . Here, we also use circuit-level simulations to understand the memory cell’s dynamics, performance limits and stability under varying pulse amplitudes.

Electrical and electronic engineering↗
DOE OSTI2022

New Total-Ionizing-Dose Resistant Data Storing Technique for NAND Flash Memory

This paper describes a new non-charge-based data storing technique in NAND flash memory called watermark that encodes read-only data in the form of physical properties of flash memory cells. Unlike traditional charge-based data storing method in flash memory, the proposed technique is resistant to total ionizing dose (TID) effects. To evaluate its resistance to irradiation effects, we analyze data stored in several commercial single-level-cell (SLC) flash memory chips from different vendors and technology nodes. These chips are irradiated using a Co-60 gamma-ray source array for up to 100 krad(Si) at Sandia National Laboratories. Experimental evaluation performed on a flash chip from Samsung shows that the intrinsic bit error rate (BER) of watermark increases from 0.8% for TID = 0 krad(Si) to 1% for TID = 100 krad(Si). Conversely, the BER of charge-based data stored on the same chip increases from 0% at TID = 0 krad(Si) to 1.5% at TID = 100 krad(Si). Overall, the results imply that the proposed technique may potentially offer significant improvements in data integrity relative to traditional charge-based data storage for very high radiation (TID > 100 krad(Si)) environments. These gains in data integrity relative to the charge-based data storage are useful in radiation-prone environments, but they come at the cost of increased write times and higher BERs before irradiation.

36 MATERIALS SCIENCE↗
DOE OSTI2020

A Dynamically-Reconfigurable Burst-Mode Link Using a Nanosecond Photonic Switch

Fast optical circuit switching has great potential to solve scaling issues with traditional packet-switch based networks and improve bandwidth and power efficiency in datacenter and high-performance computing applications. One difficultly in utilizing a fast optical switch is that the optical signal must be rapidly reacquired after each switching event so as to not significantly impact the overall throughput of the system. In this work we present a system-level integration of a nanosecond-scale $2 \times 2$ silicon photonic switch with a 25-Gbps burst-mode receiver that can lock in 31 ns. A novel FPGA-based control plane was used to generate test data, control the silicon photonic switch and burst-mode receiver, and measure bit errors at 12.5 and 20 Gbps. Error-free links (BER $< 10^{-12}$ ) with system-level reconfiguration times below 60 ns (at 20 Gbps) and 90 ns (at 12.5 Gbps) including bit- and frame-synchronization are demonstrated.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2023

Analysis and Compensation of Tx and Rx IQ Imbalances in Uplink IM-OFDMA Systems

Index modulation-based orthogonal division multiple access (IM-OFDMA) has recently been proposed as a potential technique for future wireless communication systems due to its superior spectral efficiency and error performance over conventional multiple access schemes. However, its performance is still under investigation by researchers in light of a variety of scenarios and assumptions. Following this direction, in this Article, the individual and joint effects of the transmitter (Tx) and receiver (Rx) in-phase and quadrature imbalances (IQI) on the bit-error-rate (BER) performance of the uplink IM-OFDMA scheme are investigated by considering whether each user's RF front-end is identical or not. Moreover, to reduce the detrimental effect of IQI, a preamble-based estimation and compensation method is proposed for IM-OFDMA. Closed-form expressions for the average BER of IM-OFDMA are obtained by considering the physical effect of the Tx and Rx IQI. Also, using Monte Carlo simulations, the derived expressions are verified under different system configurations. Furthermore, analytical and simulation results reveal that Tx and Rx IQI cause an error floor in the BER performance of IM-OFDMA schemes. However, the proposed estimation and compensation method not only reduces the impact of IQI but also leads to a better BER performance compared to the case of no IQI, which mainly refers to the frequency diversity caused by the IQI.

42 ENGINEERING↗
DOE OSTI2024

Testing of a Line Driver With Configurable Pre-Emphasis on Lossy Transmission Lines

Rare-event physics experiments such as the Deep Underground Neutrino Experiment (DUNE) or the next Enriched Xenon Observatory (nEXO) experiment search for rare, low-energy events, detected by sensitive detectors immersed in a cryogenic noble liquid (e.g., liquid argon or xenon). Readout electronics used within such detectors must consume minimal power while operating reliably in cryogenic environments. Furthermore, in the case of nEXO, maximizing the radiopurity of the environment is vital to minimize background noise, thus placing strict limits on the volume of dielectric materials, leading to high-loss data cables spanning distances up to 12 m. Such cables cause high attenuation and intersymbol interference (ISI), resulting in a high bit-error rate (BER). These issues were addressed by developing an integrated line driver with configurable pre-emphasis in a 65-nm CMOS process. The pre-emphasis parameters can be programmed to minimize BER for specific cables and data rates under power constraints. Here, the driver was tested at both room and cryogenic temperatures. In both cases, the output BER was found to be strongly correlated with the pre-emphasis settings. Furthermore, analysis and simulation showed that adapting the pre-emphasis settings based on the incoming bit sequence can further improve performance with minimal changes to the current solution.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

NuQKD: A Modular Quantum Key Distribution Simulation Framework for Engineering Applications

Abstract An experimental Quantum Key Distribution (QKD) implementation requires advanced costly hardware, unavailable in most research environments, making protocol testing and performance evaluation complicated. This has been a major motivation for the development of QKD simulation frameworks, to allow researchers to obtain insight before proceeding into practical implementations. Several simulators have been introduced over the recent years. However, only four are publicly available, only one of which models equipment imperfections. Currently, no open‐source simulator includes all following capabilities: channel attenuation modelling, equipment imperfections and effects on key rates, estimation of elapsed time during classical and quantum‐ channel processes, use of truly random binary sequences for qubits and measurement bases, shared ‐bit fraction customization. In this paper, we present NuQKD, an open‐ source modular, intuitive simulator, featuring all the above capabilities. NuQKD establishes communication between two computer terminals, accepts custom user inputs (iterations, raw key size, attacker interception rate etc.) and evaluates the sifted key, Quantum Bit Error Rate (QBER), elapsed communication time, and more. NuQKD capabilities include optical fiber and free ‐space simulation, modeling of equipment/channel imperfections, bitstrings from True Random Number Generators, decoy‐state protocol support, and automated evaluation of performance metrics. We expect NuQKD to enable convenient and accurate representation of actual experimental conditions.

Gkouliaras, Konstantinos↗
DOE OSTI2023

A superconducting nanowire binary shift register

We present a design for a superconducting nanowire binary shift register, which stores digital states in the form of circulating supercurrents in high-kinetic-inductance loops. Adjacent superconducting loops are connected with nanocryotrons, three-terminal electrothermal switches, and fed with an alternating two-phase clock to synchronously transfer the digital state between the loops. A two-loop serial-input shift register was fabricated with thin-film NbN and a bit error rate of less than 10 –4 was achieved, when operated at a maximum clock frequency of 83 MHz and in an out-of-plane magnetic field of up to 6 mT. A shift register based on this technology offers an integrated solution for low-power readout of superconducting nanowire single photon detector arrays and is capable of interfacing directly with room-temperature electronics and operating unshielded in high magnetic field environments.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2023

A nanocryotron memory and logic family

The development of superconducting electronics based on nanocryotrons has been limited so far to few device circuits, in part due to the lack of standard and robust logic cells. Here, we introduce and experimentally demonstrate designs for a set of nanocryotron-based building blocks that can be configured and combined to implement memory and logic functions. The devices were fabricated by patterning a single superconducting layer of niobium nitride and measured in liquid helium on a wide range of operating points. The tests show 10 - 4 bit error rates with above ± 20 % margins up to 50 MHz and the possibility of operating under the effect of an out-of-plane 36 mT magnetic field, with ± 30 % margins at 10 MHz. Additionally, we designed and measured an equivalent delay-flip-flop made of two memory cells to show the possibility of combining multiple building blocks to make larger circuits. These blocks may constitute a solid foundation for the development of nanocryotron logic circuits and finite-state machines with potential applications in the integrated processing and control of superconducting nanowire single-photon detectors.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2020

Influence of birefringent fibre joints on the visibility drift in a Mach – Zehnder interferometer

It is shown that imperfect joints of linear birefringent fibres in a fibre interferometer may result in an uncontrolled visibility drift under varying environmental conditions even with a standard phase matching device. As an example, a double Mach – Zehnder interferometer is considered, which is employed in schemes of quantum key distribution. Results of numerical simulation demonstrate the standard deviation of the quantum bit error rate (QBER), which is comparable to an average QBER value. (paper)

36 MATERIALS SCIENCE↗
DOE OSTI2021

Transmission of Images on High-Temperature Nuclear-Grade Metallic Pipe with Ultrasonic Elastic Waves

Transmission of information using elastic ultrasonic waves on existing metallic pipes provides an alternative communication option for a nuclear facility. The advantages of this approach consist of transmitting information through barriers, such as the containment building wall, with minimal modification of the existing hardware. Because bit rates on the order of kilobits per second are achievable, relatively large volumes of data, such as images, can be transmitted. A viable candidate for an ultrasonic communication channel is a stainless steel pipe of the chemical volume control system (CVCS) that penetrates through the reactor containment building wall through a sealed tunnel. To study ultrasonic communication under simulated nuclear facility conditions of high temperature, a test article was developed by installing heating tapes, temperature controllers, and thermal insulation on a laboratory CVCS-like stainless steel pipe. High temperature and radiation-resilient lithium niobate ultrasonic transducers were utilized for information transmission on the heated pipe. The amplitude shift keying (ASK) digital communication protocol was developed and implemented in a GNU Radio software-defined radio environment. A root-raised-cosine filter was introduced to suppress ultrasonic transducer ringing and thus reduce inter-symbol interference. This resulted in the enhancement of the data transmission bit rate compared to information encoding with square pulses. Demonstrations of communication at high temperature included transmission of a 90-KB image at the bit rate of 10 Kbps with a bit error rate of 10 -3 across a 6-ft-long straight pipe heated up to 230 degrees C. Additional preliminary studies were conducted to evaluate ultrasonic communication system resilience to environmental degradation and damage.

42 ENGINEERING↗
DOE OSTI2022

The Octopus processor for the CMS L1 muon trigger for High Luminosity LHC

The upgraded L1 muon trigger system of the CMS experiment in the High Luminosity Large Hadron Collider is based on custom processors featuring large Field Programmable Gate Arrays (FPGAs) connected by large numbers of optical links. These provide the I/O bandwidth and power necessary to process the complex algorithms used during the collection of physics data. The design and performance requirements of these processors creates significant challenges in signal integrity, power delivery, and thermal management. In this paper we describe the Octopus processor, featuring a large Xilinx Virtex Ultrascale+ FPGA and up to 128 links interfaced to optics through high quality twin-ax copper cables. Results on signal integrity at 25 Gb/s and the first demonstration of 50+ Gb/s links with pluggable optics in CMS are also shown, demonstrating bit error rates below 10 –15 at a 95% confidence level. The thermal performance is measured inside an Advanced-TCA crate with acceptable thermal margins up to 200 W of chip power. Future improvements are mentioned, potentially allowing operation at up to 300 W.

Instruments & Instrumentation↗
DOE OSTI2025

Development of a test system for data links of the ATLAS Inner Tracker (ITk) upgrade silicon pixel detector

This contribution introduces a novel test system developed to evaluate the signal transmission quality in high-speed data links for the 2026 Inner Tracker (ITk) upgrade of the ATLAS experiment. Using an FPGA-based data acquisition (DAQ) framework, the setup can run simultaneous Bit Error Rate (BER) tests for up to 64 channels and generate virtual eye diagrams, for qualifying the ∼26k electrical links at the ATLAS ITk data rate of 1.28 Gb/s. The paper includes results from system calibration, yielding its contribution to the measured losses, and preliminary results from tests of prototype and pre-production assemblies of on-detector links of the three ATLAS ITk Pixel subsystems.

47 OTHER INSTRUMENTATION↗