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Layout considerations for a large deep space communications antenna array are discussed. A fractal geometry for the antenna layout is described that provides optimal packing of antenna elements, efficient cable routing, and logical division of the array into identical sub-arrays.
Next generation 5G mobile architectures will take advantage of the millimeter-wave spectrum to deliver unprecedented bandwidth. Concurrently, there is a need to consolidate numerous disparate allocations into a single, multi-functional array. Existing arrays are either narrow-band, prohibitively expensive or cannot be scaled to these frequencies. In this paper, we present the first ultra-wideband millimeter-wave array to operate across the six 5G and ISM bands spanning 24-71 GHz. Critically, the array is realized using low-cost PCB. The design concept and optimized layout are presented, and fabrication and measurement considerations are discussed.
Millimeter-wave 5G mobile architectures need to consolidate disparate frequency bands into a single, multifunctional array. Existing arrays are either narrow-band, prohibitively expensive or cannot be scaled to these frequencies. In this paper, we present the first ultra-wideband millimeter wave array to operate across six 5G and ISM bands spanning 24-71 GHz. Importantly, the array is realized using low-cost PCB. The paper presents the design and optimized layout, and discusses fabrication and measurements.
The design of a wide field imaging camera suitable for use with a glancing incidence X-ray telescope is complicated by the sharply concave nature of the optimum focal surface of such a telescope. Such a camera made up of a mosaic of CCDs is being designed which is intended for flight aboard the Advanced X-ray Astrophysics Facility (AXAF). The design rationale and tradeoffs are discussed, and the layout for the imaging CCD array is presented. The related issue of optimizing performance of transmission objective gratings is also discussed, and the array of CCD orientations suitable for this problem is presented.
Two complementary MOS monolithic chip types were developed, which contain a register and multiplexer unit to be used in the central processing unit of a digital computer. The partition of the logic into a chip size consistent with the characteristics of the packages is discussed. The logic was implemented by specially configured circuitry designed to layout, as well as to optimize, performance by taking advantage of the properties of CMOS logic. Of several approaches considered for generating LSI CMOS arrays, the CMOS standard cell array design technique was selected. These design automation techniques were used to generate the chip layout, art work and working master plates, followed by the fabrication and testing of the two chip types. Sixty functional LSI arrays were delivered.
We have developed and deployed a distributed-parallel storage system (DPSS) in several high speed asynchronous transfer mode (ATM) wide area networks (WAN) testbeds to support several different types of data-intensive applications. Architecturally, the DPSS is a network striped disk array, but is fairly unique in that its implementation allows applications complete freedom to determine optimal data layout, replication and/or coding redundancy strategy, security policy, and dynamic reconfiguration. In conjunction with the DPSS, we have developed a 'top-to-bottom, end-to-end' performance monitoring and analysis methodology that has allowed us to characterize all aspects of the DPSS operating in high speed ATM networks. In particular, we have run a variety of performance monitoring experiments involving the DPSS in the MAGIC testbed, which is a large scale, high speed, ATM network and we describe our experience using the monitoring methodology to identify and correct problems that limit the performance of high speed distributed applications. Finally, the DPSS is part of an overall architecture for using high speed, WAN's for enabling the routine, location independent use of large data-objects. Since this is part of the motivation for a distributed storage system, we describe this architecture.
A pinned photodiode/interline CCD Detector Array is under development for the EOS/MODIS-T project. Outstanding features of the device include large pixels, spectrally optimized fill factors, and blooming protection. The detector has 30 spatial rows and 32 spectral columns. The device layout is split into two halves; each half has its own detector area, storage area, and output structure.
Acoustic phased array flyover noise measurements were acquired as part of the Boeing 737 MAX-7 NASA Advanced Inlet Liner segment of the Quiet Technology Demonstrator 3 (QTD3) flight test program. This paper reports on the processes used for separating and quantifying the engine inlet, exhaust and airframe noise source components and provides sample phased array-based comparisons of the component noise source levels associated with the inlet liner treatment configurations. Full scale flyover noise testing of NASA advanced inlet liners was conducted as part of the Quiet Technology Demonstrator 3 flight test program in July and August of 2018. Details on the inlet designs and testing are provided in the companion paper of Reference 1. The present paper provides supplemental details relating to the acoustic phased array portion of the analyses provided in Ref. 1. In brief, the test article was a Boeing 737MAX-7 aircraft with a modified right hand (starboard side) engine inlet, which consisted of either a production inlet liner, a NASA designed inlet liner or a simulated hard wall configuration (accomplished by applying speed tape over the inlet acoustic treatment areas). In all three configurations, the engine forward fan case acoustic panel was replaced with a unperforated (hardwall) panel. No other modifications to any other acoustic treatment areas were made. The left hand (port side) engine was a production engine and was flown at idle thrust for all measurements in order to isolate the effects of the inlet liners to the right hand engine. As described in Ref. 1, the NASA inlet treatment consists of laterally cut slots (cut perpendicular to the flow direction) which are designed to reduce excrescence drag while maintaining or exceeding the liner acoustic noise reduction capabilities. The NASA inlet liner consists of a Multi-Degree of Freedom (MDOF) design with two breathable septum layers inserted into each honeycomb cell [1]. The aircraft noise measurements were acquired for both takeoff (flaps 1 setting, gear up) and approach (flaps 30 gear up and gear down) configurations. The inlet and flight test configurations are summarized in Table 1. Table 1: Inlet Treatment and Flight Configurations Inlet Forward Fan Case Aircraft Production Hardwall Flaps 1, gear up; flaps 30 gear up; flaps 30 gear down NASA Hardwall Flaps 1, gear up; flaps 30 gear up; flaps 30 gear down Hardwall Hardwall Flaps 1, gear up; flaps 30 gear up; flaps 30 gear down III.Test Description and Hardware The flight testing was conducted at the Grant County airport in Moses Lake, WA, between 27 July and 6 August 2018. The noise measurement instrumentation included 8 flush dish microphones arranged in a noise certification configuration as well as an 840 microphone phased array. The flush dish microphones were used to quantify the levels and differences in levels between the various inlet treatments. The phased array was used to separate and quantify the narrowband (tonal) and broadband noise component levels from the engine inlet/exhaust and from the airframe. Phased array extraction of the broadband component was critical to this study because it allowed for the separation of the inlet component from the total airplane level noise even when it was significantly below the total level. Figure 1 provides an overview of the phased array microphone layout as well as a detailed image of an individual phased array microphone mounted in a plate holder (the microphone sensor is the dot in the center of the plate). The ground plane ensemble array microphones (referred to as “ensemble array” in this paper) were mounted in plates with “flower petal” edges designed to minimize edge scattering effects. Fig. 1 Flyover test microphone layout. The phased array configuration was the result of a progressive development of concepts originally implemented in Ref. 2 and refined over the following years, consisting namely of multiple multi-arm logarithmic spiral subarrays designed to cover overlapping frequency ranges and optimized for various aircraft emission angles. For the present case, the signals from all 840 microphones were acquired on a single system. The 840 microphones were parsed into 11 primary subarray sets spanning from smallest to largest aperture size and labeled accordingly as “a, b, …, k”, where “a” corresponds to the smallest fielded subarray and “k” corresponds to the largest aperture subarray. The apertures ranged from approximately 10 ft to 427 ft in size (in the flight direction) with the subarrays consisting of between 215 and 312 microphones. Figure 2 shows three such subarrays, k, h and a. As done in Ref. 2, microphones were shared between subarrays in order to reduce total channel count. Fig. 2 Sample subarray sizes (20° from overhead – refer to Figure 3a discussion). In addition to the above, each of the 11 primary subarray sets consisted of four subarrays optimized to provide near equivalent array spatial resolution in both the flight and lateral directions within 30 degrees of overhead (i.e., airplane directly above the center of the array), namely, at angles of 0, ±10, ±20 and ±30 degrees relative to overhead where angle is defined as shown in Figure 3a. This allowed for optimized aircraft noise measurements from 60 to 120 degree emission angle.6 An example of this pletharray design is shown in Figure 3b for the k subarray. When the aircraft is at overhead, the microphones indicated by the blue markers are used for beamforming. When the aircraft is at angles ±10 degrees from overhead, both the blue and red colored microphones are used, and so on for the ±20 and ±30 degree aircraft locations. See Ref. 3 for extensive details on pletharray design for aeroacoustic phased array testing. 6 In the discussions that follow, emission angle values are used. These are the angles at the time sound is emitted relative to the engine axis and are calculated based on flight path angle, body aircraft body angle with respect to the relative wind direction, and engine axis angle relative to aircraft body angle.
Using the backscatter ultraviolet instrument (BUV) aboard NIMBUS 4 as a baseline, point scanner mechanisms and spatial multiplex scanning systems were compared on the basis of sensitivity, field of view and simplicity. This comparison included both spectral and spatial scanning and multiplexing techniques. The selected system which optimally met the performance requirements for a shuttle based instrument was a pushbroom spatial scanner using a 15 element photomultiplier tube array and a Hadamard multiplex spectral scan. The selected system was conceptually designed. This design includes ray traces of the monochromator, mechanical layouts and the electronic block diagram.
This paper proposes a model for a miniaturized signal conditioning system for biopotential and ion-selective electrode arrays. The system consists of three main components: sensors, interconnections, and signal conditioning chip. The model for this system is based on SPICE. Transmission-line based equivalent circuits are used to represent the sensors, lumped resistance-capacitance circuits describe the interconnections, and a model for the signal conditioning chip is extracted from its layout. A system for measurements of biopotentials and ionic activities can be miniaturized and optimized for cardiovascular applications based on the development of an integrated SPICE system model of its electrochemical, interconnection, and electronic components.
The cost of several circuit configurations for large (5MW) array fields were investigated to assess the relative costs of high and low voltage configurations. Three source circuit NOC voltages were evaluated: 400V (ungrounded), 800V (+ or 400V center grounded), and 2000V (+ or - 1000V center grounded). Four source circuit configurations were considered for each of the three NOC voltages. The configurations correspond to source circuit currents of 15, 30, 45, and 60 amperes, respectively. Conceptual layouts for 5MW building blocks for each of the above configurations were developed. The designs were optimized to minimize BOS electrical and structural costs. Only the BOS electrical costs were evaluated. The designs were broken down into the following elements for cost: (1) basic source circuit intermodule wiring, bypass diodes and associated hardware, source circuit to J-Box wiring, etc; (2) J-Box blocking diodes, varistors, heat sinks, and housing; (3) disconnects source circuit disconnects, fuses, and housing; (4) bus cabling J-Box to PCU interface wiring, and trenching; (5) interface bus bar, group disconnects, and fuses; and (6) fault detection shunts, signal wire, electronics, and alarm. It is concluded that high voltage low current circuits are not economical, at higher currents high and low voltage circuit costs approach each other, high voltage circuits are not likely to offer near term advantage, and development work/manufacturer stimulation is needed to develop low cost high voltage hardware.
The pace of progress in the design of integrated circuits continues to amaze observers inside and outside of the industry. Three decades ago, a 50 transistor chip was a technological wonder. Fifteen year later, a 5000 transistor device would 'wow' the crowds. Today, 50,000 transistor chips will earn a 'not too bad' assessment, but it takes 500,000 to really leave an impression. In 1975 a typical ASIC device had 1000 transistors, took one year to first samples (and two years to production) and sold for about 5 cents per transistor. Today's 50,000 transistor gate array takes about 4 months from spec to silicon, works the first time, and sells for about 0.02 cents per transistor. Fifteen years ago, the single most laborious and error prone step in IC design was the physical layout. Today, most IC's never see the hand of a layout designer: and automatic place and route tool converts the engineer's computer captured schematic to a complete physical design using a gate array or a library of standard cells also created by software rather than by designers. CAD has also been a generous benefactor to the digital design process. The architect of today's digital systems creates the design using an RTL or other high level simulator. Then the designer pushes a button to invoke the logic synthesizer-optimizer tool. A fault analyzer checks the result for testability and suggests where scan based cells will improve test coverage. One obstinate holdout amidst this parade of progress is the automation of analog design and its reduction to semi-custom techniques. This paper investigates the application of CAD techniques to analog design.
The NASA John H. Glenn Research Center has developed a revolutionary 32 in. diameter Levitated Ducted Fan (LDF) conceptual design. The objective of this work is to develop a viable non-contact propulsion system utilizing Halbach arrays for all-electric flight, and many other applications. This concept will help to reduce harmful emissions, reduce the Nation s dependence on fossil fuels, and mitigate many of the concerns and limitations encountered in conventional aircraft propulsors. The physical layout consists of a ducted fan drum rotor with blades attached at the outer diameter and supported by a stress tuner ring at the inner diameter. The rotor is contained within a stator. This concept exploits the unique physical dimensions and large available surface area to optimize a custom, integrated, electromagnetic system that provides both the levitation and propulsion functions. The rotor is driven by modulated electromagnetic fields between the rotor and the stator. When set in motion, the time varying magnetic fields interact with passive coils in the stator assembly to produce repulsive forces between the stator and the rotor providing magnetic suspension. LDF can provide significant improvements in aviation efficiency, reliability, and safety, and has potential application in ultra-efficient motors, computers, and space power systems.
We describe performance of large-scale arrays of metallic magnetic calorimeters (MMCs) we are developing to meet requirements of the Lynx X-ray Microcalorimeter (LXM) instrument in the astrophysics mission concept Lynx. We have fabricated prototypes with 55,800 x-ray pixels thermally connected to 5,688 MMC sensors. Subarrays demonstrate three types of pixels, which have different energy and spatial resolution goals in LXM. Pixel pitch is 50 or 25 µm. For two subarrays, use of position sensitive detectors, in a "hydra" configuration with 25 x-ray absorbers per sensor, helps achieve a large focal plane by increasing pixel count relative to readout channels. Since each absorber has a different thermal link to its sensor, it generates a different pulse shape and enables discrimination of pixel position. Superconducting wiring from all sensors was brought out to the perimeter of the overall array using multiple buried metal layers planarized by Chemical Mechanical Planarization to achieve high critical current, low inductance, and high fabrication yield. An automated, algorithmic approach was used to layout the complex wiring pattern. For readout with existing small arrays of Superconducting Quantum Interference (SQUID) amplifiers, 112 selected pixels were connected to wire bond pads. In hydras, we successfully identified 25 pulse shapes using rise-time and pulse height. Pulse shapes were similar to simulations. We measured noise and responsivity to substrate temperature and applied x-ray pulses. While we designed sensors to have high inductance to relative to stray inductance of wiring, we had only mismatched (lower input inductance) SQUIDs available in our current apparatus, giving non-optimized resolution. We compared measured and calculated energy resolutions. We have the required sensitivity to reach < 3 eV FWHM resolution for 6 keV x-rays, required for the LXM Main Array, and the ability to discriminate the 25 different absorber pixels down to energies < 300 eV.
This paper presents selected features of a human factors oriented plan for a Space Station Freedom (SSF) ground Discipline Operations Center (DOC) that is integrated with other work areas used by multidisciplinary life scientists. This combined facility is referred to as an integrated DOC or IDOC. This plan is based upon the assumption that there will be a constantly changing array of specialized equipment and procedures used by life sciences principal investigators (PI) on the ground which must be linked to SSF through various DOC systems. Other sites will also be able to communicate with SSF (Anon., 1992). It is also assumed that cost reduction will be a major design consideration and that one integrated structure will be less expensive to build and operate than two separate ones. Since both the DOC personnel and PIs will need to communicate with the flight crew aboard SSF, the general interconnect architecture of the PIs' communication linkage is considered here. Key human factor design elements of this plan include: a candidate facility layout which accommodates three (3), multipurpose, rapidly reconfigurable work areas (suites) and consequent user traffic flow considerations, a multimedia telecommunications support capability, functional (human) traffic flow, optimized internal illumination and acoustics requirements, selected volumetric and safety requirements, and other architectural design parameters.