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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Pareto Optimization of Analog Circuits Using Reinforcement Learning

Analog circuit optimization and design presents a unique set of challenges in the IC design process. Many applications require the designer to optimize for multiple competing objectives, which poses a crucial challenge. Motivated by these practical aspects, we propose a novel method to tackle multi-objective optimization for analog circuit design in continuous action spaces. In particular, we propose to (i) extrapolate current techniques in Multi-Objective Reinforcement Learning to continuous state and action spaces and (ii) provide for a dynamically tunable trained model to query user defined preferences in multi-objective optimization in the analog circuit design context.

99 GENERAL AND MISCELLANEOUS↗
DOE OSTI2026

Towards Generalizable and Efficient Circuit Topology Design: A Graph-Transformer-based Surrogate Model with Curriculum Learning

Unlike circuit parameter and sizing optimizations, the automated design of analog circuit topologies poses significant challenges for learning-based approaches. One challenge arises from the combinatorial growth of the topology space with circuit size, which limits the topology optimization efficiency. Moreover, traditional circuit evaluation methods are time-consuming, while the presence of data discontinuity in the topology space makes the accurate prediction of circuit performance exceptionally difficult for unseen topologies. To tackle these challenges, we design a novel Graph-Transformer-based Network (GTN) as the surrogate model for circuit evaluation, offering a substantial acceleration in the speed of circuit topology optimization without sacrificing performance. Our GTN model architecture is designed to embed voltage changes in circuit loops and current flows in connected devices, enabling accurate performance predictions for circuits with unseen topologies. To address the cold start problem when scaling GTN to large-scale circuits, we further introduce a curriculum learning strategy that progressively trains GTN from small-scale to large-scale circuits. This approach enables the model to first learn fundamental physical principles from simpler topologies and gradually adapt to complex configurations, effectively bridging the circuit complexity gap and improving prediction accuracy. Taking the power converter circuit design as an experimental task, our GTN model significantly outperforms an analytical approach and baseline methods directly utilizing graph neural networks. Furthermore, GTN achieves less than 5% relative error and 196× speed-up compared with high-fidelity simulation. Notably, our GTN surrogate model empowers an automatic circuit design framework to discover circuits of comparable quality to those identified through high-fidelity simulation while reducing the time required by up to 98.2%. With curriculum learning, the enhanced GTN achieves a 51% improvement for performance prediction of large-scale circuits compared to the GTN model without this strategy. These advancements establish GTN as a scalable framework for automated analog circuit design across varying circuit complexity levels.

Lu, Haoshu [New Jersey Institute of Technology (NJ↗
DOE OSTI2021

Radio frequency mixing modules for superconducting qubit room temperature control systems

As the number of qubits in nascent quantum processing units increases, the connectorized RF (radio frequency) analog circuits used in first generation experiments become exceedingly complex. The physical size, cost, and electrical failure rate all become limiting factors in the extensibility of control systems. We have developed a series of compact RF mixing boards to address this challenge by integrating I/Q quadrature mixing, intermediate frequency/LO (local oscillator)/RF power level adjustments, and direct current bias fine tuning on a 40 × 80 mm 2 four-layer printed circuit board with electromagnetic interference shielding. The RF mixing module is designed to work with RF and LO frequencies between 2.5 and 8.5 GHz. The typical image rejection and adjacent channel isolation are measured to be ~27 dBc and ~50 dB. By scanning the drive phase in a loopback test, the module short-term amplitude and phase linearity are typically measured to be 5 ×10 -4 (V pp /V mean ) and 1 ×10 -3 radian (pk-pk). The operation of the RF mixing board was validated by integrating it into the room temperature control system of a superconducting quantum processor and executing randomized benchmarking characterization of single and two qubit gates. We measured a single-qubit process infidelity of 9.3(3) × 10 -4 and a two-qubit process infidelity of 2.7(1) × 10 -2 .

47 OTHER INSTRUMENTATION↗
DOE OSTI2021

Analysis and mitigation of parasitic resistance effects for analog in-memory neural network acceleration

To support the increasing demands for efficient deep neural network processing, accelerators based on analog in-memory computation of matrix multiplication have recently gained significant attention for reducing the energy of neural network inference. However, analog processing within memory arrays must contend with the issue of parasitic voltage drops across the metal interconnects, which distort the results of the computation and limit the array size. This work analyzes how parasitic resistance affects the end-to-end inference accuracy of state-of-the-art convolutional neural networks, and comprehensively studies how various design decisions at the device, circuit, architecture, and algorithm levels affect the system's sensitivity to parasitic resistance effects. Here, a set of guidelines are provided for how to design analog accelerator hardware that is intrinsically robust to parasitic resistance, without any explicit compensation or re-training of the network parameters.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Embedded Fluidic Sensing and Control with Soft Open‐Cell Foams

Abstract The synthesis of soft matter intelligence with circuit‐driven logic has enabled a new class of robots that perform complex tasks or conform to specialized form factors in unique ways that cannot be realized through conventional designs. Translating this hybrid approach to fluidic systems, the present work addresses the need for sheet‐based circuit materials by leveraging the innate porosity of foam—a soft material—to develop pneumatic components that support digital logic, mixed‐signal control, and analog force sensing in wearables and soft robots. Analytical tools and experimental techniques developed in this work serve to elucidate compressible gas flow through porous sheets, and to inform the design of centimeter‐sized foam resistors with fluidic resistances on the order of 10 9 Pa s m −3 . When embedded inside soft robots and wearables, these resistors facilitate diverse functionalities spanning both sensing and control domains, including digital logic using textile logic gates, digital‐to‐analog signal conversion using ladder networks, and analog sensing of forces up to 40 N via compression‐induced changes in resistance. By combining features of both circuit‐based and materials‐based approaches, foam‐enabled fluidic circuits serve as a useful paradigm for future hybrid robotic architectures that fully embody the sensing and computing capabilities of soft fluidic materials.

Rajappan, Anoop↗
DOE OSTI2024

ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade

We present the design and characterization of the first fullchain precision timing prototype ASIC, named ETL Readout Chipversion 1 (ETROC1) for the CMS MTD endcap timing layer (ETL)upgrade. The ETL utilizes Low Gain Avalanche Diode (LGAD) sensors todetect charged particles, with the goal to achieve a time resolutionof 40–50 ps per hit, and 30–40 ps per track with hits from twodetector layers. The ETROC1 is composed of a 5 × 5 pixelarray and peripheral circuits. The pixel array includes a4 × 4 active pixel array with an H-tree shaped networkdelivering clock and charge injection signals. Each active pixel iscomposed of various components, including a bump pad, a chargeinjection circuit, a pre-amplifier, a discriminator, adigital-to-analog converter, and a time-to-digital converter. Thesecomponents play essential roles as the front-end link in processingLGAD signals and measuring timing-related information. Theperipheral circuits provide clock signals and readoutfunctionalities. The size of the ETROC1 chip is7 mm× 9 mm. ETROC1 has been fabricated in a 65 nmCMOS process, and extensively tested under stimuli of chargeinjection, infrared laser, and proton beam. The time resolution ofbump-bonded ETROC1 + LGAD chipsets reaches 42–46 ps per hit in thebeam test.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Training self-learning circuits for power-efficient solutions

As the size and ubiquity of artificial intelligence and computational machine learning models grow, the energy required to train and use them is rapidly becoming economically and environmentally unsustainable. Recent laboratory prototypes of self-learning electronic circuits, such as “physical learning machines,” open the door to analog hardware that directly employs physics to learn desired functions from examples at a low energy cost. In this work, we show that this hardware platform allows for an even further reduction in energy consumption by using good initial conditions and a new learning algorithm. Using analytical calculations, simulations, and experiments, we show that a trade-off emerges when learning dynamics attempt to minimize both the error and the power consumption of the solution—greater power reductions can be achieved at the cost of decreasing solution accuracy. Finally, we demonstrate a practical procedure to weigh the relative importance of error and power minimization, improving the power efficiency given a specific tolerance to error.

Stern, Menachem (ORCID:0000000302158082)↗
DOE OSTI2021

Approximate Bacon-Shor code and holography

We explicitly construct a class of holographic quantum error correction codes with non-trivial centers in the code subalgebra. Specifically, we use the Bacon-Shor codes and perfect tensors to construct a gauge code (or a stabilizer code with gauge-fixing), which we call the holographic hybrid code. This code admits a local log-depth encoding/decoding circuit, and can be represented as a holographic tensor network which satisfies an analog of the Ryu-Takayanagi formula and reproduces features of the sub-region duality. We then construct approximate versions of the holographic hybrid codes by “skewing” the code subspace, where the size of skewing is analogous to the size of the gravitational constant in holography. These approximate hybrid codes are not necessarily stabilizer codes, but they can be expressed as the superposition of holographic tensor networks that are stabilizer codes. For such constructions, different logical states, representing different bulk matter content, can “back-react” on the emergent geometry, resembling a key feature of gravity. The locality of the bulk degrees of freedom becomes subspace-dependent and approximate. Such subspace-dependence is manifest from the point of view of the “entanglement wedge” and bulk operator reconstruction from the boundary. Exact complementary error correction breaks down for certain bipartition of the boundary degrees of freedom; however, a limited, state-dependent form is preserved for particular subspaces. We also construct an example where the connected two-point correlation functions can have a power-law decay. Coupled with known constraints from holography, a weakly back-reacting bulk also forces these skewed tensor network models to the “large N limit” where they are built by concatenating a large N number of copies.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2026

Digital Silicon Photomultiplier Chip Testing

Silicon Photomultipliers (SiPMs) are highly sensitive photodetectors. Traditional analog SiPMs require complex external readout electronics. Digital SiPMs (dSiPMs) include digital readout circuitry directly on-chip, offering superior timing resolution, reduced power consumption and compact size, pixel-level masking for active noise reduction. The primary objectives of this study are to, verify digital logic integrity of the shift registers used for controlling the pixel masking circuit, and determine the dark count rate of individual pixels as a function of bias voltage and clock frequency. I observe and explain behavior of the shift register and counting circuit.

Graham, Bennett [U. Chicago (main)]↗
DOE OSTI2020

Quantum neuromorphic computing

Quantum neuromorphic computing physically implements neural networks in brain-inspired quantum hardware to speed up their computation. In this perspective article, we show that this emerging paradigm could make the best use of the existing and near future intermediate size quantum computers. Some approaches are based on parametrized quantum circuits and use neural network-inspired algorithms to train them. Other approaches, closer to classical neuromorphic computing, take advantage of the physical properties of quantum oscillator assemblies to mimic neurons and synapses to compute. In this work, we discuss the different implementations of quantum neuromorphic networks with digital and analog circuits, highlight their respective advantages, and review exciting recent experimental results.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Porphene and porphite as porphyrin analogs of graphene and graphite

Two-dimensional materials have unusual properties and promise applications in nanoelectronics, spintronics, photonics, (electro)catalysis, separations, and elsewhere. Most are inorganic and their properties are difficult to tune. Here we report the preparation of Zn porphene, a member of the previously only hypothetical organic metalloporphene family. Similar to graphene, these also are fully conjugated two-dimensional polymers, but are composed of fused metalloporphyrin rings. Zn porphene is synthesized on water surface by two-dimensional oxidative polymerization of a Langmuir layer of Zn porphyrin with K 2 IrCl 6 , reminiscent of known one-dimensional polymerization of pyrroles. It is transferable to other substrates and bridges μm-sized pits. Contrary to previous theoretical predictions of metallic conductivity, it is a p-type semiconductor due to a predicted Peierls distortion of its unit cell from square to rectangular, analogous to the appearance of bond-length alternation in antiaromatic molecules. The observed reversible insertion of various metal ions, possibly carrying a fifth or sixth ligand, promises tunability and even patterning of circuits on an atomic canvas without removing any π centers from conjugation.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Evaluation of an event-driven 3FI ASIC for spectroscopic X-ray detection with synchrotron radiation

The novel design and evaluation on the NSLS-II beamline of the 3FI application-specific integrated circuit (ASIC) bump-bonded to a simple, planar, 2D segmented silicon sensor are presented. The ASIC was developed for full-field fluorescence spectral X-ray imaging (3FI). It is a small-scale prototype that features a square array of 32 × 32 pixels, and the size of the pixels is 100 µm × 100 µm. The ASIC was implemented in a 65 nm CMOS integrated circuit fabrication process. Each pixel incorporates a charge-sensitive amplifier, a shaping filter, a discriminator, a peak detector and a sample-and-hold circuit, allowing detection of events and storage of signal amplitudes. The system operates in a frameless event-driven readout mode, outputting analog values for threshold-triggered events, allowing high-speed multi-element X-ray fluorescence data acquisition. The 3FI ASIC achieves per-channel spectrometric performance at a power consumption of only 200 µW per pixel, with nearly all dissipation confined to the analog front-end. An energy resolution is measured at the level of 308 eV full width at half-maximum (FWHM) at 8.04 keV (Cu Kα), and 138 eV FWHM at 3.69 keV (Ca Kα). This per-pixel capability makes the prototype suitable for in situ trace element microanalysis in biological and environmental studies. Moreover, the frameless architecture of the detector is designed to address limitations of conventional X-ray fluorescence microscopy, which typically requires mechanical scanning, by enabling continuous high-throughput data acquisition in future full-field implementations.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Playing Nonlocal Games across a Topological Phase Transition on a Quantum Computer

Many-body quantum games provide a natural perspective on phases of matter in quantum hardware, crisply relating the quantum correlations inherent in phases of matter to the securing of quantum advantage at a device-oriented task. In this Letter, we introduce a family of multiplayer quantum games for which topologically ordered phases of matter are a resource yielding quantum advantage. Unlike previous examples, quantum advantage persists away from the exactly solvable point and is robust to arbitrary local perturbations, irrespective of system size. We demonstrate this robustness experimentally on Quantinuum’s H1-1 quantum computer by playing the game with a continuous family of randomly deformed toric code states that can be created with constant-depth circuits leveraging midcircuit measurements and unitary feedback. We are thus able to tune through a topological phase transition—witnessed by the loss of robust quantum advantage—on currently available quantum hardware. This behavior is contrasted with an analogous family of deformed Greenberger-Horne-Zeilinger states, for which arbitrarily weak local perturbations destroy quantum advantage in the thermodynamic limit. Lastly, we discuss a topological interpretation of the game, which leads to a natural generalization involving an arbitrary number of players.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Measurement-induced multipartite-entanglement regimes in collective spin systems

We study the competing effects of collective generalized measurements and interaction-induced scrambling in the dynamics of an ensemble of spin-1/2 particles at the level of quantum trajectories. This setup can be considered as analogous to the one leading to measurement-induced transitions in quantum circuits. We show that the interplay between collective unitary dynamics and measurements leads to three regimes of the average Quantum Fisher Information (QFI), which is a witness of multipartite entanglement, as a function of the monitoring strength. While both weak and strong measurements lead to extensive QFI density (i.e., individual quantum trajectories yield states displaying Heisenberg scaling), an intermediate regime of classical-like states emerges for all system sizes where the measurement effectively competes with the scrambling dynamics and precludes the development of quantum correlations, leading to sub-Heisenberg-limited states. We characterize these regimes and the crossovers between them using numerical and analytical tools, and discuss the connections between our findings, entanglement phases in monitored many-body systems, and the quantum-to-classical transition.

Physics↗
DOE OSTI2024

The SparkPix-S ASIC for the sparsified readout of 1 MHz frame-rate X-ray cameras at LCLS-II: pixel design and simulation results

Exploiting the “sparse” nature of the information in XPCS (X-ray Photon Correlation Spectroscopy) and XSVS (Speckle Visibility Spectroscopy) experiments, we present the SparkPix-S, a 3-sides buttable Application Specific Integrated Circuit (ASIC) based on a sparsified readout strategy for large-format hybrid detectors. The SparkPix-S architecture, based on the successful ePix family, will be composed as follows: a front-end 2-D matrix of 384×352 square pixels with 50 µm pitch is arranged to match the dimensions of a PIN Si-sensor matrix; charge readout, signal shaping and amplitude discrimination is performed at pixel-level, by means of a low-power (<18 µW) analog processor, which, in case of an event, negotiates access to an analog bus placed every other column; on the chip periphery (balcony), the information on each bus is digitized by an array of successive approximation analog-to-digital converters (SAR-ADCs) running at 10 Msps; on the digital back-end the global logic will generate the output data stream using low-voltage differential signalling (LVDS). A first prototype of the SparkPix-S, with a reduced matrix size of 96×96 pixels, is currently under production on a 130 nm CMOS technology. Simulated performance results show an equivalent noise charge <60 el. r.m.s. at 1 MHz repetition rate, with a maximum input energy of 60 keV and capability to discriminate charge signals with equivalent energy as low as 900 eV.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

A pixel detector ROIC with a 3-bit, 40 Msps synchronous ADC per pixel for HL LHC

The prototype Fermi Compact Muon Solenoid (CMS) Pixel (FCP130), manufactured in a 130 nm process, is a readout integrated circuit (ROIC) designed for the High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 48 × 160 pixels, each 100 × 30 μm2 in size. Each pixel contains a charge sensitive preamplifier with self-biasing leakage current compensation, eight auto-zero comparators and a Gray code encoder for a 3-bit flash-type ADC. The total power consumption is approximately 24 μW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 80 e- with threshold dispersion < 110 e-RMS, which allows an in-time threshold setting of ~ 1000 e-.

43 PARTICLE ACCELERATORS↗
DOE OSTI2023

In-Pixel Readout IC with compact in-pixel ADC for Pixel detectors at HL LHC

The prototype Smart Pixel concept test chip (SP28), designed in a CMOS 28 nm bulk process, is a proof of concept readout integrated circuit (ROIC) designed for a future Phase III High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events and pileup insensitivity, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 32 × 16 pixels, each 25 × 25 µm 2 in size. Each pixel contains a charge sensitive preamplifer with leakage current compensation, three auto-zero comparators for a 2-bit fash-type ADC. The total power consumption is approximately 5 µW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 90 e- with threshold dispersion < 45 e-RMS, which allows an in-time threshold setting of ≈ 475 e-.

Parpillon, Benjamin↗
DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 $\mu$m$^2$ in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e$^-$ and a total dispersion of $\sim$100e$^-$ The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4% - 75.4% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm$^2$ staying within the experimental constraints.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗