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DOE OSTI2025

Inverse Segmented Motor Drive Using Dual ANPC Inverters for Common-Mode Voltage and Neutral-Point Current Cancellation

This article proposes an inverse segmented motor drive (SgMD) utilizing dual active neutral point clamped (ANPC) inverters. In the proposed configuration, the neutral point current and common-mode (CM) voltage is topologically canceled, achieving zero total neutral point current and CM voltage under ideal conditions. Also, the zero total neutral point current minimizes the neutral point voltage imbalance in ANPC inverters. The mechanisms behind neutral point current and CM voltage cancellation in the proposed inverse SgMD are first introduced. The modifications to the motor windings for implementing the inverse SgMD are explained, showing that a standard motor can be readily adapted for the proposed configuration. A space vector modulation (SVM) scheme tailored for the proposed topology is presented, along with a carrier-based implementation. Simulation results validate that the proposed topology can achieve zero total CM voltage and neutral point current. It is also shown that the proposed inverse SgMD can reduce neutral point voltage fluctuation by about 90% and RMS current stress in the dc-link capacitors by about 43% compared to the conventional SgMD.

Lee, Sangwhee [ORNL] (ORCID:0000000335490057)↗
DOE OSTI2025

A Digital Three Level Space Vector Modulator for High Frequency Vector Sequence Generation

This letter proposes a digital high-speed three-level space vector pulse width modulator (3L-SVPWM). A conventional 3L-SVPWM is typically computation-based, involving a sequential execution of sub-tasks on a digital signal processor (DSP) based controller. The resulting high computation time of 5.4 μs limits the implementation of additional control blocks for switching frequencies greater than 100 kHz. This is overcome by transforming sub-tasks into digital blocks with 1-0 decisions and simpler arithmetic operations. The sub-task blocks are executed concurrently on a programmable logic device (PLD). Hence, a fast 3L-SVPWM execution in 140 ns is achieved. The proposed digital 3L-SVPWM enables high switching frequency operation of wide bandgap (WBG) device-based 3 L inverters to generate high fundamental frequency waveforms. A finite state machine is an integral part of the proposed implementation with the ability to generate any vector sequence, maximizing the usage of redundant vector states in 3L-SVPWM. Here, the proposed digital 3L-SVPWM operation is demonstrated with a GaN-based 3 L active neutral point clamped (3L-ANPC) inverter. Experimental results are presented at 250 kHz switching frequency to generate vector sequences for center-aligned SVPWM (CA-SVPWM) and common mode voltage reduced SVPWM (CMVR-SVPWM). The results also showcase a high fundamental frequency generation capability of 10 kHz.

active neutral point clamped inverter↗
DOE OSTI2024

Postfault Operation of Three-Level Inverter Driven Six-Phase PMSM With Enhanced Torque–Speed Region

This article presents an open-switch postfault operational technique with enhanced torque–speed region for three-level (3L) active neutral point clamped (ANPC) inverter-driven symmetrical six-phase (SSP) permanent magnet synchronous machines (PMSMs). Maximum torque (MT), minimum loss (ML), and single three-phase (STP) operations are commonly used for the postfault operations of six-phase drives. The maximum possible torque and speed in these operations are generally limited by voltage, current ratings, and the neutral point configuration of the motor. To enhance the postfault torque and speed operating region, the torque and speed limits in different postfault operational techniques are determined based on the voltage, current constraints, and neutral point configuration of the SSP-PMSM. In this work, a unified postfault operation is proposed that increases the postfault operational limits by combining MT, ML, and STP operations and modifying the neutral point configuration of the SSP-PMSM. In addition, a technique is also presented that modifies the pulsewidth modulation technique to enable full torque operation below 0.5 p.u. speed. The proposed postfault operational technique enables full-speed (1 p.u.) operation by operating in STP mode and full torque operation (1 p.u.) below 0.5 p.u. speed. Furthermore, the postfault operational technique is experimentally validated using a Gallium Nitride (GaN) device-based3L-ANPC inverter-driven SSP-PMSM.

42 ENGINEERING↗