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Inverse Segmented Motor Drive Using Dual ANPC Inverters for Common-Mode Voltage and Neutral-Point Current Cancellation
This article proposes an inverse segmented motor drive (SgMD) utilizing dual active neutral point clamped (ANPC) inverters. In the proposed configuration, the neutral point current and common-mode (CM) voltage is topologically canceled, achieving zero total neutral point current and CM voltage under ideal conditions. Also, the zero total neutral point current minimizes the neutral point voltage imbalance in ANPC inverters. The mechanisms behind neutral point current and CM voltage cancellation in the proposed inverse SgMD are first introduced. The modifications to the motor windings for implementing the inverse SgMD are explained, showing that a standard motor can be readily adapted for the proposed configuration. A space vector modulation (SVM) scheme tailored for the proposed topology is presented, along with a carrier-based implementation. Simulation results validate that the proposed topology can achieve zero total CM voltage and neutral point current. It is also shown that the proposed inverse SgMD can reduce neutral point voltage fluctuation by about 90% and RMS current stress in the dc-link capacitors by about 43% compared to the conventional SgMD.
Switching Modes for Reduction of Peak Voltage Transients in GaN-Based Three Level ANPC Inverter
The switching pole voltage can transition between P,0, and N states in a three-level active neutral point clamped (ANPC) inverter. State transitions between 0-P and 0-N can be realized with different switching modes. Three switching modes- Short 1 , Short 2 , and Full are studied considering the effect of capacitive current paths. The role of clamping and inner switch on/off conditions is determined using simplified equivalent circuit models. Short 2 with clamping switch off is beneficial for turn-on overvoltage suppression but results in high turn-off overvoltage. Full mode with a parallel current sharing path is effective for turn-off overvoltage suppression but leads to high turn-on overvoltage. Hence, a Modified Full mode is proposed to achieve the simultaneous objective of overvoltage suppression at both turn-on and turn-off transient during high load currents. This benefits 3L ANPC operation at a low power factor with a high load current at fundamental voltage zero crossing points. Here, a 650V GaN-based three-level ANPC inverter prototype is designed and used to evaluate the switching modes and overvoltage suppression strategies through double pulse tests and continuous operation.
A Six-Phase Space Vector PWM Technique for Wide Bandgap Device-Based Three-Level Inverters
This article presents a space vector pulsewidth modulation (SVPWM) technique for wide bandgap (WBG) device-based three-level (3L) six-phase inverters. Implementation of the SVPWM techniques for any six-phase inverter is complex for its high number of possible voltage vectors. Different six-phase load configurations are also possible depending on the angle between two consecutive phases and neutral point connections. The implementation techniques change depending on the load configuration. Moreover, a common neutral point for all six phases leads to circulating currents. Capacitor voltage balancing is also needed for 3L inverters. Capacitor voltage balancing and addressing the circulating current problem further increases the implementation complexity. In this article, a generalized SVPWM technique is proposed for the six-phase 3L inverters that is implementable using two three-phase 3L SVPWM blocks. The SVPWM technique also ensures dc bus capacitor voltage balancing and minimizes circulating current. Here, the SVPWM technique is experimentally verified using a GaN-based 3L six-phase active neutral point clamped (ANPC) inverter prototype, and the results are presented in this article.
A Real-Time ANPC Inverter Digital Twin with Integrated Design-For-Trust
The demand for renewable energy has increased over the last few years, and so has the demand for greater expectations within the energy market. This increasing trend has been accompanied by more significant usage of internet-connected devices (IoT), leading to critical electrical infrastructure being connected to the internet. Implementing internet connectivity with such devices and systems provides benefits such as improving the system's performance, facilitating irregularity and anomaly mitigation, and providing additional situational awareness for enhanced decision-making. However, enhancing the connected system with IoT introduces a drawback – a greater vulnerability to cyber-attacks. Cyber-attacks targeting critical infrastructure in the electrical sector have occurred in the United States and Ukraine. These cyber-attacks highlight and expose vulnerabilities that a system inherits when connecting to the internet. These attacks left thousands of customers without electricity for hours until operators could regain control of the electric utility grid. Therefore, to address the vulnerabilities of an internet-connected power electronic device, this work focused on the hardware layer of the system. Implementing a cyber-control system inside the hardware layer can significantly reduce the possibility of an attacker patching malicious controller firmware into a photovoltaic grid-connected inverter, thus mitigating the likelihood that the inverter becomes inactive a cyber-attack scenario. With this mitigation technique, if a cyberattack is successful and an attacker gains control of the network, a cyber-defense technique is in place to mitigate the impact of the cyber-attack. This additional protection layer was developed based on an innovative concept known as Digital Twin (DT). A DT, in this case, replicates an Active-Neutral Point Clamped (ANPC) inverter and was designed using a hardware language known as VHDL (Very High-Speed Integrated Circuit Hardware Description Language) and applied to Field-Programmable-GateArray (FPGA). The DT is embedded within the FPGA and contained in a controller board, the UCB (Unified Controller Board), developed by the University of Arkansas electrical engineering team. This UCB also contains two Digital Signal Processors (DSPs) responsible for generating associated signals to control an authentic physical inverter. These DSP signals are received and processed by the FPGA that implements the DT of an ANPC; in other words, it simulates in realtime the expected output of an actual ANPC inverter using the signals from the DSP. When a new firmware is ready to be patched, the DT provides output signals simulating behavior that a real ANPC inverter would generate with the new firmware. The new firmware is tested to check if it meets all the operational requirements established using a Design-For-Trust technique (DFTr). If the new firmware fails in at least one of the DFT tests, it is considered malicious and must be rejected. This work is divided into sections, such as Background, which explains the pieces that were used and the strategy behind this work; Process and Procedure, which explains the methodology that was adopted to prove the reliability and effectiveness of this work; Results and Discussion, where the simulations and results are described and explained; followed by Conclusion and Future work section, which concludes this work and adds possible future projects to continue this work further.
Digital Twin of an ANPC inverter with integrated Design-For-Trust
Reducing costs and increasing manufacturing output while creating reliable products are three essential components needed to keep a business competitive. In the past, having an asset that could address these three challenges at the same time would be challenging. However, recent advances in computer processing capabilities coupled with increases to network speeds allowed such a system to become possible; and this is known as a Digital Twin (DT), which represents a virtual copy of a production system or a product. Here, this work exhibits a DT application of an Active Neutral Point Clamped (ANPC) inverter using a controller. The controller emulates the ANPC responses of a new Digital Signal Processing (DSP) firmware and validates this new firmware by using Design-For-Trust (DFTr) characteristics. If the new firmware is malicious, then it should be rejected, thus adding preemptive protection measures for inverter based distributed energy resources.
A Voltage Injection-Based Current Harmonics Suppression Strategy for Six-Phase PMSM With Nonsinusoidal Back EMF
This article presents a voltage injection-based current harmonic minimization method for wide bandgap device-based six-phase permanent magnet synchronous machine (PMSM) drives. The presence of low-order harmonics is common in the back EMF of PMSMs with low slot and high pole numbers. The back EMF harmonics generate low-order harmonic currents that increase torque ripples. Furthermore, zero-sequence current (ZSC) is also observed if all six phases are connected to a common neutral point. ZSC does not affect the torque ripple but reduces the system efficiency. A special technique is required to reduce ZSC for variable speed drives as direct ac component to synchronous reference frame (SRF) dc transformation is not possible for ZSC. In this article, a voltage injection-based current harmonics reduction method is proposed. The injected harmonic voltage coefficients are calculated from the harmonic estimations of back EMF and updated using closed-loop harmonic compensators to improve steady-state performance. For ZSC reduction, third harmonics power controller, and for 6n ± 1 (n = 1, 2,...) order harmonic current reduction, SRF current controllers are presented in this article. Furthermore, the current harmonics minimization method is experimentally verified using a GaN-based three-level active neutral point clamped inverter-driven six-phase PMSM.
A Digital Three Level Space Vector Modulator for High Frequency Vector Sequence Generation
This letter proposes a digital high-speed three-level space vector pulse width modulator (3L-SVPWM). A conventional 3L-SVPWM is typically computation-based, involving a sequential execution of sub-tasks on a digital signal processor (DSP) based controller. The resulting high computation time of 5.4 μs limits the implementation of additional control blocks for switching frequencies greater than 100 kHz. This is overcome by transforming sub-tasks into digital blocks with 1-0 decisions and simpler arithmetic operations. The sub-task blocks are executed concurrently on a programmable logic device (PLD). Hence, a fast 3L-SVPWM execution in 140 ns is achieved. The proposed digital 3L-SVPWM enables high switching frequency operation of wide bandgap (WBG) device-based 3 L inverters to generate high fundamental frequency waveforms. A finite state machine is an integral part of the proposed implementation with the ability to generate any vector sequence, maximizing the usage of redundant vector states in 3L-SVPWM. Here, the proposed digital 3L-SVPWM operation is demonstrated with a GaN-based 3 L active neutral point clamped (3L-ANPC) inverter. Experimental results are presented at 250 kHz switching frequency to generate vector sequences for center-aligned SVPWM (CA-SVPWM) and common mode voltage reduced SVPWM (CMVR-SVPWM). The results also showcase a high fundamental frequency generation capability of 10 kHz.
Postfault Operation of Three-Level Inverter Driven Six-Phase PMSM With Enhanced Torque–Speed Region
This article presents an open-switch postfault operational technique with enhanced torque–speed region for three-level (3L) active neutral point clamped (ANPC) inverter-driven symmetrical six-phase (SSP) permanent magnet synchronous machines (PMSMs). Maximum torque (MT), minimum loss (ML), and single three-phase (STP) operations are commonly used for the postfault operations of six-phase drives. The maximum possible torque and speed in these operations are generally limited by voltage, current ratings, and the neutral point configuration of the motor. To enhance the postfault torque and speed operating region, the torque and speed limits in different postfault operational techniques are determined based on the voltage, current constraints, and neutral point configuration of the SSP-PMSM. In this work, a unified postfault operation is proposed that increases the postfault operational limits by combining MT, ML, and STP operations and modifying the neutral point configuration of the SSP-PMSM. In addition, a technique is also presented that modifies the pulsewidth modulation technique to enable full torque operation below 0.5 p.u. speed. The proposed postfault operational technique enables full-speed (1 p.u.) operation by operating in STP mode and full torque operation (1 p.u.) below 0.5 p.u. speed. Furthermore, the postfault operational technique is experimentally validated using a Gallium Nitride (GaN) device-based3L-ANPC inverter-driven SSP-PMSM.
Power Layout Design of a GaN HEMTs-Based High-Power High-Efficiency Three-Level ANPC Inverter for 800 V DC Bus System
Multiple commutation paths exist for switching devices in a three-level active neutral point clamped (3L-ANPC) inverter operation based on the selected switching state and current direction. In addition, the capacitive coupling path of the nonswitching device is a key design aspect for enabling high voltage and high current operation of gallium nitride (GaN) switches in 3L-ANPC topology. A comprehensive study of the switching transient events of inner, outer, and clamping devices of 3L-ANPC is presented in this article. The commutation mechanisms for worst-case transient voltage overshoots (TVOs) are identified. A simplified equivalent circuit model is presented to determine the design criteria for the power layout structure's parasitic inductances. A power layout strategy satisfying the design criteria is then proposed using an insulated metal substrate power printed circuit board (PCB) to enable efficient high-power operation. The proposed design minimizes the commutation and capacitive coupling path inductances to 6 nH and 11.5 nH, respectively. This enables the fast switching operation of GaN HEMTs at 800 V dc, 36 A with a low TVO of 31% verified through experimental three-level double pulse test results. Experimental evaluation of a three-phase 3L-ANPC hardware prototype based on the proposed power layout shows 99% efficiency at 800 V, 9.5 kVA and 50 kHz switching frequency. The proposed design achieves a low case-to-ambient thermal resistance of 2.3 °C/W.
Implementing a Hardware Testbed Using 3-Level ANPC Software Defined Inverters for Fault Analysis of a Transmission Network
In this paper, we propose the implementation of a hardware testbed using 3-level active neutral point clamped (ANPC) software-defined inverters for fault analysis. A test case transmission network equipped with two grid forming (GFM) inverters and four resistive loads is considered in this research. Firstly, grid forming control laws including PI feedback control and droop control are implemented to operate the inverters in parallel. Then, we implement a fault ride-through (FRT) logic and perform a simulation of the test system by applying a three-phase fault. Simulation results show the effectiveness of the fault recovery algorithm upon clearance of the fault. Finally, a 3-level ANPC software-defined inverter is programmed with required control laws and characterized through various lab experiments.