Quantum enhanced Josephson junction field-effect transistors for logic applications
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Pan, W. (ORCID:0000000256295296)↗
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Recent advancements in chiral spintronics: from molecular-level insights to device applications. A prospect based on the interplay between physical and chemical properties of chiral systems
This review discusses recent advancements in chiral-based spin-electronic devices achieved using suitable combinations of organic, inorganic and hybrid materials. The focus is on how chirality can be effectively used to control spin in practical applications, particularly in spintronic sensors and consumer devices. Interestingly, the underlying mechanism for this control is the chiral-induced spin selectivity (CISS) effect, which links the structural chirality of a material to its spin-selective electronic transport properties. The CISS effect arises from the observation that charge transmission in chiral systems is spin selective. Experimental evidence suggests a relationship between electron spin and the structural handedness of the material. In conclusion, this unique structure-transport relationship can be exploited to design a wide range of spintronics devices, including memory, transistors, logic gates and molecular q-bits.
37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
Atomically Precise Graphene Nanoribbon Transistors with Long-Term Stability and Reliability
Atomically precise graphene nanoribbons (GNRs) synthesized from the bottom-up exhibit promising electronic properties for high-performance field-effect transistors (FETs). The feasibility of fabricating FETs with GNRs (GNRFETs) has been demonstrated, with ongoing efforts aimed at further improving their performance. However, their long-term stability and reliability remain unexplored, which is as important as their performance for practical applications. In this work, we fabricated short-channel FETs with nine-atom-wide armchair GNRs (9-AGNRFETs). We revealed that the on-state (/ ON ) current performance of the 9-AGNRFETs deteriorates significantly over consecutive full transistor on and off logic cycles, which has neither been demonstrated nor previously considered. To address this issue, we deposited a thin ~10 nm thick atomic layer deposition (ALD) layer of aluminum oxide (Al 2 O 3 ) directly on these devices. The integrity, compatibility, electrical performance, stability, and reliability, of the GNRFETs before and/or after Al 2 O 3 deposition were comprehensively studied. The results indicate that the observed decline in electrical device performance is most likely due to the degradation of contact resistance over multiple measurement cycles. We successfully demonstrated that the devices with the Al 2 O 3 layer operate well up to several thousand continuous full cycles without any degradation. Our study offers valuable insights into the stability and reliability of GNR transistors, which could facilitate their large-scale integration into practical applications.
36 MATERIALS SCIENCE↗
Space-Charge-Limited van der Waals Spin Transistor
Integrating semiconducting and magnetic materials could combine transistorlike operation with nonvolatility and enable architectures such as logic in memory. Here, in this work, we employ correlated electrical transport and scanning nitrogen-vacancy center magnetic imaging to elucidate a spin transistor concept that amalgamates vertical and lateral hopping transport inside a 2D antiferromagnetic semiconductor, mechanistically distinct from vertical tunneling devices. Our device, based on a monolayer-bilayer junction in CrSBr, displays giant, gate-tunable magnetoresistance driven by the dual action of electrostatic doping on space-charge-limited lateral conduction and interlayer exchange coupling. Moreover, we visualize a field-trainable, layer-sharing effect that selects between coherent or domain-wall reversal at the spin-flip transition, enabling multilevel, memristive conductance states. Our layer-dependent space charge mechanism for convergent electrical and magnetic control opens opportunities to address limitations in contemporary computing.
2-dimensional systems↗
A nanoscale photonic thermal transistor for sub-second heat flow switching
Abstract Control of heat flow is critical for thermal logic devices and thermal management and has been explored theoretically. However, experimental progress on active control of heat flow has been limited. Here, we describe a nanoscale radiative thermal transistor that comprises of a hot source and a cold drain (both are ~250 nm-thick silicon nitride membranes), which are analogous to the source and drain electrodes of a transistor. The source and drain are in close proximity to a vanadium oxide (VO x )-based planar gate electrode, whose dielectric properties can be adjusted by changing its temperature. We demonstrate that when the gate is located close ( < ~1 µm) to the source-drain device and undergoes a metal-insulator transition, the radiative heat transfer between the source and drain can be changed by a factor of three. More importantly, our nanomembrane-based thermal transistor features fast switching times ( ~ 500 ms as opposed to minutes for past three-terminal thermal transistors) due to its small thermal mass. Our experiments are supported by detailed calculations that highlight the mechanism of thermal modulation. We anticipate that the advances reported here will open new opportunities for designing thermal circuits or thermal logic devices for advanced thermal management.
42 ENGINEERING↗
Enhancing mobility and interface state engineering via UV-ozone treatment in BEOL-compatible ultrathin TiO 2 transistors
It has emerged as a potential candidate to improve the performance of monolithic-three-dimensional (M3D) integration of fused logic and memories through low-temperature in situ synthesis of high-performance metal–oxide–semiconductor (MOS) transistors. Here, we report the demonstration of the BEOL-compatible low thermal budget (350 °C) fabrication process of ultrathin-TiO2 transistors by the combination of RTA and UV-ozone treatment (RTA-UVOz). UV–ozone (UVOz) treatment of TiO2 anatase films significantly enhances stability, boosting ION current and field effect mobility (μ FE ) by two times of magnitude in TiO2 TFTs. UV ozone treatment helps to eliminate pre-existing oxygen vacancies and carbon contamination on TiO2 channels even at low temperature (100 °C), resulting in high-quality channel/dielectric interfaces with low interface states (D it ). During UVOz treatment, oxygen species (O x ) passivate the oxygen vacancies ($V$$^{2+}_{o}$), and hence low concentration of $V$$^{2+}_{o}$ would be left for ionization/de-ionization under PBS/NBS, leading to improved bias stress stability. Furthermore, the TiO 2 TFTs with thin ZrO 2 gate dielectric exhibited excellent performance including a lower subthreshold swing (SS) of 98 mV/dec with high drive I ON current ∼ 4.5 μA/μm, a high I ON /I OFF > 10 9 , and mobility μFE of 7 cm 2 /V-s under a battery powered voltage of 1 V. UV–ozone treatment enables high-performance, CMOS-compatible TiO 2 transistors with a low thermal budget, ideal for next-generation flexible, energy-efficient electronics.
BEOL↗
Analog-to-digital converter based on voltage-controlled superconducting devices
The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.
Analog-to-digital converter↗
Ambipolar Transport in Polycrystalline GeSn Transistors for Complementary Metal-Oxide-Semiconductor Applications
Group-IV alloy GeSn is a promising material for electronic and optoelectronic applications due to its compatibility with both Si substrates and established Si fabrication processes. This study focuses on polycrystalline GeSn (10% Sn), which offers a cost-effective, large-area, and versatile alternative to epitaxial GeSn. We demonstrate ambipolar transport behavior in polycrystalline GeSn thin film transistors, achieving electron and hole field-effect mobilities reaching up to 0.05 cm 2 /Vs and 2.05 cm 2 /Vs, respectively. Through temperature-dependent analysis, we elucidate the underlying mechanism of this phenomenon, which we attribute to quantum tunneling between the Schottky barrier contact and the channel, as well as potential barriers between the grain boundaries of this polycrystalline film, thereby advancing the understanding of polycrystalline GeSn's electrical properties. Furthermore, this work highlights the potential of ambipolar transport as a technique to employ towards the development of GeSn complementary metal-oxide-semiconductor field-effect transistors, promising to simplify and reduce the cost of GeSn manufacturing processes for edge computing and sensing applications.
42 ENGINEERING↗
Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs
Ferroelectric random access memory (FeRAM) is a promising candidate for energy-efficient nonvolatile memory, particularly for logic-in-memory and compute-in-memory (CIM) applications. Among the available cell architectures, One-Transistor–n-Capacitor (1T-nC) and two-transistor–n-capacitor (2T-nC) FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study of these two architectures under both dimensional scaling ( XY/Z shrinkage) and vertical integration (increasing stacked capacitors per cell). Using technology computer-aided design (TCAD) and circuit-level simulations, we analyze how scaling impacts ferroelectric capacitance, parasitic coupling, and floating-node (FN) dynamics, which together dictate sense margin (SM) and read stability. A key mitigation strategy—floating unselected capacitors—is applied to both architectures, effectively decoupling the SM from the number of stacked capacitors and enabling tractable analysis across scaling regimes. Results show that 1T-nC suffers more from charge sharing with the bitline (BL), while 2T-nC benefits from transistor isolation and stronger low-voltage sensing at the cost of increased area. By systematically evaluating these behaviors across scaling directions, this work establishes the reliability trade-offs of 1T-nC and 2T-nC cells and provides design guidelines for high-density, vertically integrated FeRAM systems.
1T-nC↗
Reconfigurable neuromorphic components and algorithms for next-generation artificial intelligence
Digital transistor-based general-purpose hardware (e.g., central processing units) is the dominant solution to support both traditional computing (logic, arithmetic, etc.) as well as modern artificial intelligence. State-of-the-art research has shown feasibility of post-digital physics-based neuromorphic hardware, which is hypothesized to support artificial intelligence algorithms with orders-of-magnitude improved time/energy efficiencies. But such research has not been widely deployed mainly because of such novel hardware’s extreme application-specificity, and the dominance of low-cost general-purpose (but inefficient) digital hardware. To make use of the novel algorithms and the superlative performance of physics-based hardware, we need to identify scientific principles that can enable generality in physics-based hardware. This work resulted in two important broad outcomes – first, we demonstrate fully reconfigurable neuromorphic components, and second, we demonstrate a viable artificial intelligence learning algorithm that can exploit the functioning of neuromorphic hardware. We demonstrate up to five orders of magnitude improvement in energy efficiency compared to the best general-purpose digital hardware.
97 MATHEMATICS AND COMPUTING↗
Superionic fluoride gate dielectrics with low diffusion barrier for two-dimensional electronics
Exploration of new dielectrics with a large capacitive coupling is an essential topic in modern electronics when conventional dielectrics suffer from the leakage issue near the breakdown limit. Here, to address this looming challenge, we demonstrate that rare-earth metal fluorides with extremely low ion migration barriers can generally exhibit an excellent capacitive coupling over 20 μF cm -2 (with an equivalent oxide thickness of ~0.15 nm and a large effective dielectric constant near 30) and great compatibility with scalable device manufacturing processes. Such a static dielectric capability of superionic fluorides is exemplified by MoS 2 transistors exhibiting high on/off current ratios over 10 8 , ultralow subthreshold swing of 65 mV dec -1 and ultralow leakage current density of ~10 -6 A cm -2 . Therefore, the fluoride-gated logic inverters can achieve notably higher static voltage gain values (surpassing ~167) compared with a conventional dielectric. Furthermore, the application of fluoride gating enables the demonstration of NAND, NOR, AND and OR logic circuits with low static energy consumption. In particular, the superconductor–insulator transition at the clean-limit Bi 2 Sr 2 CaCu 2 O 8+δ can also be realized through fluoride gating. In conclusion, our findings highlight fluoride dielectrics as a pioneering platform for advanced electronic applications and for tailoring emergent electronic states in condensed matter.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
Identification and mitigation of memory block timing issue in ITk ABCStar during ASIC production
The ABCStar is a mixed-signal front-end readout ASIC for the strips sensor portion of the ATLAS ITk detector being developed as part of the High-Luminosity LHC upgrade. In pre-production testing, a subtle design flaw was uncovered in the ABCStar that was reducing wafer yields in some manufactured lots from the expected 90% to as low as 2%. The root cause was determined to be a timing issue in the logic synthesized to control previously silicon proven memory blocks re-used for this ASIC. The solutions proposed included manufacturing process changes by the wafer foundry, changes to the operating parameters for the ABCStar in the detector, and the possibility that a redesign might be required. The two mitigation efforts were undertaken in parallel, with the process modification route a less desirable solution since already manufactured wafers would need to be scrapped in favour of the new ones. Based on a knowledge of the existing process, and testing done on the worst performing wafers, it was proposed that raising the core operating voltage of the ABCStar from 1.20V to 1.25V could address the timing issue by sufficiently speeding up its transistors. An extensive testing program that included the effects of temperature and radiation expected over the lifetime of the ITk detector was conducted to validate that approach. Those tests and studies proved that even the worst performing wafers would have yields over 80% with the 1.25V core voltage, and neither the modified process nor redesign would be required for ensuring reliable operation of the ITk. Based on testing, a further timing mitigation was implemented to provide an additional margin of reliability by increasing the duty cycle of the clock to the ABCStar. Testing of all ABCStar wafers has been completed and the production of the detector modules using these ASICs is now well underway as a result of the efforts detailed herein.
FOS: Physical sciences↗
ALD-Derived WO 3– x Leads to Nearly Wake-Up-Free Ferroelectric Hf 0.5 Zr 0.5 O 2 at Elevated Temperatures
Breaking the memory wall in advanced computing architectures will require complex 3D integration of emerging memory materials such as ferroelectrics─either within the back-end-of-line (BEOL) of CMOS front-end processes or through advanced 3D packaging technologies. Achieving this integration demands that memory materials exhibit high thermal resilience, with the capability to operate reliably at elevated temperatures, such as 125°C, due to the substantial heat generated by front-end transistors. However, silicon-compatible HfO 2 -based ferroelectrics tend to exhibit antiferroelectric-like behavior in this temperature range, accompanied by a more pronounced wake-up effect, posing significant challenges to their thermal reliability. Here, we report that by introducing a thin tungsten oxide (WO 3–x ) layer─known as an oxygen reservoir─and carefully tuning its oxygen content, ultrathin Hf 0.5 Zr 0.5 O 2 (5 nm) films can be made robust against the ferroelectric-to-antiferroelectric transition at elevated temperatures. This approach not only minimizes polarization loss in the pristine state but also effectively suppresses the wake-up effect, reducing the required wake-up cycles from 10 5 to only 10 at 125°C, a qualifying temperature for back-end memory integrated with front-end logic, as defined by the JEDEC standard. First-principles density functional theory (DFT) calculations reveal that WO 3 enhances the stability of the ferroelectric orthorhombic phase (o-phase) at elevated temperatures by increasing the tetragonal-to-orthorhombic phase energy gap and promoting favorable phonon mode evolution, thereby supporting o-phase formation under both thermodynamic and kinetic constraints.
36 MATERIALS SCIENCE↗
Cryogenic-Refined MOSFET Modeling for Oscillator, Frequency Divider, and Amplifier Designs Below 4 K
Capturing device characteristic changes at cryogenic temperatures is crucial for cryo-CMOS circuit designs. In this work, we present an isothermal cryogenic-refined modeling approach for CMOS transistors that is simple, low overhead, and easy to implement while offering the required accuracy for predicting circuit performance at the designated temperatures. Guided by die-level measurement data and circuit design principles, the model introduces corrections to only five critical parameters: threshold voltage, carrier mobility, elevated low-frequency flicker noise, dominant high-frequency shot noise, and subthreshold swing (SS). These refinements are implemented around the foundry-provided SPICE model, which is typically validated only down to about 200 K. With these adjustments, the proposed cryogenic-refined model achieves less than 5% error in both large-signal metrics (I–V characteristics) and small-signal parameters (e.g., transconductance) when compared with device measurements at deep-cryogenic temperatures. The methodology is validated in two advanced technologies: TSMC 40-nm CMOS and GlobalFoundries (GF) 45-nm RF-SOI. We further demonstrate its applicability in three representative RF circuits: a 30-GHz LC oscillator, a high-speed current-mode-logic (CML) frequency divider (FD), and a subthreshold Gb/s amplifier, all showing close agreement between simulated predictions and measurements performed at 4 and 2.5 K. Finally, we believe that the proposed approach is implementation-friendly and can significantly accelerate the development of cryo-CMOS integrated circuits.
circuit modeling↗