MICROPOWER TRANSISTOR LOGIC CIRCUITS
Micropower transistor logic circuits for spaceborne computers
COMPUTER↗
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Complementary transistor-transistor logic /CTTL/ - An approach to high-speed micropower logic.
Description of a new approach to micropower integrated circuits that is called complementary transistor-transistor logic (CTTL). This logic combines the inherent low standby power of a complementary inverter with the high speed of the TTL-type input. Results of monolithic fabricated circuits are presented. These circuits are shown to be equally adaptable to hybrid and discrete circuitry.
Stehlin, R. A.↗
Synthesis of current-switching circuits with cell matching using p-n-p and n-p-n transistors
Logical circuit for analysis of switching circuits with cell matching using p-n-p and n-p-n transistors
TRANSISTOR↗
Improved micropower logic circuits
Micropower transistor logic circuits designed to operate from power supply voltages which vary with temperature
TEMPERATURE EFFECT↗
Lower power levels for logic microcircuits.
Low power similar transistor logic microcircuits to minimize power drain through gating options
Sturman, J. C.↗
Delay analysis of combinations of pass transistors and classical logic gates
Combinations of pass transistors and logic gates driving nonlinear capacitive loads are analyzed for the presence of characteristics that will permit easier and more accurate digital logic simulation. Accurate time delay models are developed by studying the nature of the response of simplified circuit models to variations of input waveform rise and fall times and output loading. The nonlinear effects of the CMOS logic devices are minimized to permit easier interpretation of the influence of nonlinear capacitive loads. The performance of a CMOS inverter with a complex nonlinear load consisting of a pass transistor that separates a range of capacitances is compared to the same inverter circuit with a linear capacitive load to develop an understanding of the unique requirements of modeling a nonlinear system. Several methods of modeling the delay of CMOS circuits are reviewed, and a multi-parameter linear model is described. General guidelines for designing CMOS circuits with complex load circuits are developed, emphasizing that the circuit output rise delays and fall delays must be separately analyzed.
Gibson, Jonathan S.↗
Quantum enhanced Josephson junction field-effect transistors for logic applications
Not Available
Pan, W. (ORCID:0000000256295296)↗
Asynchronous sequential circuit design using pass transistor iterative logic arrays
The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circuits. This is the first ILA architecture for sequential circuits reported in the literature. The ILA architecture produces a very regular circuit structure. Moreover, it is immune to both 1-1 and 0-0 crossovers and is free of hazards. This paper also presents a new critical race free STT state assignment which produces a simple form of design equations that greatly simplifies the ILA realizations.
Liu, M. N.↗
Silicon Carbide Junction Field Effect Transistor Digital Logic Gates Demonstrated at 600 deg. C
The High Temperature Integrated Electronics and Sensors (HTIES) Program at the NASA Lewis Research Center is currently developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. The HTIES team recently fabricated and demonstrated the first semiconductor digital logic gates ever to function at 600 C.
Neudeck, Philip G.↗
The Design of Fault Tolerant Quantum Dot Cellular Automata Based Logic
As transistor geometries are reduced, quantum effects begin to dominate device performance. At some point, transistors cease to have the properties that make them useful computational components. New computing elements must be developed in order to keep pace with Moore s Law. Quantum dot cellular automata (QCA) represent an alternative paradigm to transistor-based logic. QCA architectures that are robust to manufacturing tolerances and defects must be developed. We are developing software that allows the exploration of fault tolerant QCA gate architectures by automating the specification, simulation, analysis and documentation processes.
Armstrong, C. Duane↗
Micropower complementary logic.
Low power consumption of complementary resistor- diode-transistor logic /CRDTL/ circuits
INTEGRATED CIRCUIT↗
High-speed micropower microelectronic logic circuits Final technical documentary report, 18 May 1967 - 18 Jun. 1968
High speed micropower microelectronic transistor logic circuits in integrated form
Stehlin, R.↗
Pass transistor implementations of multivalued logic
A simple straight-forward Karnaugh map logic design procedure for realization of multiple-valued logic circuits is presented in this paper. Pass transistor logic gates are used to realize multiple-valued networks. This work is an extension of pass transistor implementations for binary-valued logic.
Maki, G.↗
Event-Driven Random-Access-Windowing CCD Imaging System
A charge-coupled-device (CCD) based high-speed imaging system, called a realtime, event-driven (RARE) camera, is undergoing development. This camera is capable of readout from multiple subwindows [also known as regions of interest (ROIs)] within the CCD field of view. Both the sizes and the locations of the ROIs can be controlled in real time and can be changed at the camera frame rate. The predecessor of this camera was described in High-Frame-Rate CCD Camera Having Subwindow Capability (NPO- 30564) NASA Tech Briefs, Vol. 26, No. 12 (December 2002), page 26. The architecture of the prior camera requires tight coupling between camera control logic and an external host computer that provides commands for camera operation and processes pixels from the camera. This tight coupling limits the attainable frame rate and functionality of the camera. The design of the present camera loosens this coupling to increase the achievable frame rate and functionality. From a host computer perspective, the readout operation in the prior camera was defined on a per-line basis; in this camera, it is defined on a per-ROI basis. In addition, the camera includes internal timing circuitry. This combination of features enables real-time, event-driven operation for adaptive control of the camera. Hence, this camera is well suited for applications requiring autonomous control of multiple ROIs to track multiple targets moving throughout the CCD field of view. Additionally, by eliminating the need for control intervention by the host computer during the pixel readout, the present design reduces ROI-readout times to attain higher frame rates. This camera (see figure) includes an imager card consisting of a commercial CCD imager and two signal-processor chips. The imager card converts transistor/ transistor-logic (TTL)-level signals from a field programmable gate array (FPGA) controller card. These signals are transmitted to the imager card via a low-voltage differential signaling (LVDS) cable assembly. The FPGA controller card is connected to the host computer via a standard peripheral component interface (PCI).
Monacos, Steve↗
Recent advancements in chiral spintronics: from molecular-level insights to device applications. A prospect based on the interplay between physical and chemical properties of chiral systems
This review discusses recent advancements in chiral-based spin-electronic devices achieved using suitable combinations of organic, inorganic and hybrid materials. The focus is on how chirality can be effectively used to control spin in practical applications, particularly in spintronic sensors and consumer devices. Interestingly, the underlying mechanism for this control is the chiral-induced spin selectivity (CISS) effect, which links the structural chirality of a material to its spin-selective electronic transport properties. The CISS effect arises from the observation that charge transmission in chiral systems is spin selective. Experimental evidence suggests a relationship between electron spin and the structural handedness of the material. In conclusion, this unique structure-transport relationship can be exploited to design a wide range of spintronics devices, including memory, transistors, logic gates and molecular q-bits.
37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
High isolation RF signal selection switches
A selection switch with high isolation between RF signal input terminals is achieved with a gated Schmitt trigger circuit feeding into a control NAND gate in each signal switching channel. The control NAND gates of the separate signal channels are coupled to an output terminal by a single NAND gate. The schmitt trigger circuits and all gates are implemented with Schottky transistor-transistor logic circuits having input clamping diodes. Each Schmitt trigger circuit includes two cascaded NAND gates and a feedback isolation Schottky diode between one input terminal connected to receive an RF input and another input terminal connected to receive a feedback signal from the second of the two cascaded NAND gates. Both NAND gates of the Schmitt trigger circuits are enabled by the same switch control signal which enables the control gates.
Hanna, M. F.↗
A 100-kHz frequency divider, distribution amplifier
A frequency divider, distribution amplifier module having low phase noise and low phase drift with temperature and high isolation between outputs was developed for use in the hydrogen maser frequency standard, where it divides 1 MHz from the previous frequency divider down to 100 kHz and provides four transistor-transistor logic (TTL) outputs.
Lutes, G.↗
Cyclic and low temperature effects on microcircuits
Cyclic temperature and low temperature operating life tests, and pre-/post-life device evaluations were used to determine the degrading effects of thermal environments on microcircuit reliability. Low power transistor-transistor-logic gates and linear devices were included in each test group. Device metallization systems included aluminum metallization/aluminum wire, aluminum metallization/gold wire, and gold metallization/gold wire. Fewer than 2% electrical failures were observed during the cyclic and low temperature life tests and the post-life evaluations revealed approximately 2% bond pull failures. Reconstruction of aluminum die metallization was observed in all devices and the severity of the reconstruction appeared to be directly related to the magnitude of the temperature excursion. All types of bonds except the gold/gold bonds were weakened by exposure to repeated cyclic temperature stress.
Weissflug, V. A.↗